Switched-capacitor Networks Research Articles

Single source self balanced switched capacitor based singe phase nine level inverter

Multilevel inverters are becoming increasingly significant due to their ability to efficiently convert power in various applications such as renewable energy systems, electric vehicles (EVs), and industrial drives. The growing need for efficient power conversion in these areas has driven heightened interest in multilevel inverters. High inrush current is required for numerous applications, including variable frequency drives, single-phase or three-phase machine drives, locomotives, electric vehicles. However, managing this inrush current is crucial to prevent damage to the power source and other connected equipment, as well as to ensure smooth and reliable operation. The solution for this is to provide isolation between load and source. The proposed single phase switched capacitor multilevel inverter possess the feature of virtual isolation between the load and the source. This topology consists of a switched capacitor cell network and a multilevel inverter. In this work, a simplest architecture is used for the MLI section to reduce the number of switches. The MLI section consists of only eight switches. Although the switched capacitor network in this topology consists of a higher number of switches, the switches in the network carry only very low current, resulting in negligible losses. Additionally, the switched capacitor network is highly modular in nature. The proposed single-phase inverter can be converted to a three-phase multilevel inverter (MLI) by connecting identical units in each phase, with the reference sinewave signal for the pulse-width modulation technique derived from the corresponding phases. Consequently, this proposed topology is suitable for both low-power and high-power applications. This work demonstrates that self-voltage balancing of the level capacitors can be achieved without the need for auxiliary components.In this design, the level capacitors act as the source to the load and are charged through switched capacitors. The voltage THD in the suggested work is less than 5%, which is in accordance with IEEE 519 standards. High voltage gain, better load, and line regulation, are other significant advantages of this novel topology. Another feature of this work is simplicity in design and can be easily extended to higher voltage levels. Comprehensive simulation and experimental results are provided to validate the precise performance of the proposed multilevel inverter

The Symmetric Dual Inductor Hybrid Converter for Direct 48V-to-PoL Conversion

This work introduces the symmetric dual inductor hybrid (SDIH) dc-dc converter topology, which is suitable for large conversion ratios where regulation is required, such as direct 48 V to point-of-load (PoL) applications. A dickson-type switched capacitor network is used to effectively produce two interleaved PWM outputs with a greatly reduced voltage amplitude relative to the input voltage, allowing the subsequent magnetic volume to be reduced while retaining modest switching frequencies. Distinct from related variations, part count is significantly reduced while both even and odd order switched capacitor networks can be used with straightforward split-phase control; allowing either network type to achieve complete soft-charging of all flying capacitors. Additionally, charge flow is uniformly distributed through all elements, with equal capacitor and inductor values being preferred. Subsequently this topology is expected to simplify component selection, improve electrical and thermal performance, and reduce cost. Furthermore, analysis is presented that calculates precise phase durations without making small ripple assumptions, revealing up to a 75% timing error in cases where either inductor or capacitor ripple is ignored. Finally, a discrete prototype validates this analysis and demonstrates very high measured power densities of 1,029 W/in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{3}$</tex-math></inline-formula> , 754 W/in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{3}$</tex-math></inline-formula> , and 663 W/in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{3}$</tex-math></inline-formula> for 48 V input and regulated output voltages of 3 V, 2 V, and 1 V, respectively, while switching at a frequency of 750 kHz.

A switched-inductor switched-capacitor based ultra-gain boost converter: analysis and design

A feature known as high-voltage gain conversion is necessary for a number of applications, including photovoltaic (PV) connected systems, UPS, SMPS, and some inverter applications, specifically for the power processing of low-voltage renewable sources. This article makes a suggestion for an ultra-gain boost converter based on a switched-inductor switched-capacitor (SISC) network. Ultra-voltage gain (&gt; 15) and lower voltage stresses across the switches are the main benefits of the proposed converter. Additionally, compared with other high-gain topologies, the number of components decreases. This paper presents a systematic analysis of the proposed ultra-gain boost DC–DC converter along with a comparison to other topologies that have been previously published in the literature. The simulation model confirmed that the efficiency of the proposed topology is 95.23%.

Constant Frequency CC-CV Operation of Isolated LLC Resonant DC-DC Converter Using Switched Capacitor Network for WCS

Constant Frequency CC-CV Operation of Isolated LLC Resonant DC-DC Converter Using Switched Capacitor Network for WCS

Transformerless bidirectional switched-inductor switched-capacitor converter

ABSTRACT This research presents a unique bidirectional converter based on the active switched-inductor and switched-capacitor networks of the ASL-SU2C converter. The converter’s primary advantages are its high voltage gain and reduced switch stress. This was accomplished by the converter using three inductors, two switched-capacitors, two switches, and diodes. Switches are used in place of diodes to enable bidirectional power flow in the proposed work, and synchronous rectification is used to boost efficiency by reducing conduction losses. Two inductors and two switches on the low voltage side of the converter aid in lowering the average switch current and, consequently, the current stress. The control operation is made simpler by the fact that two switches on the high voltage side (HVS) have one duty cycle and the other two switches on the low voltage side (LVS) have a different duty cycle. Consequently, two switches will always have identical duty cycles. In order to validate the theoretical findings, the performance of the transformerless bidirectional switched-inductor switched-capacitor (TBSISC) topology is examined in steady state, compared to that of other bidirectional converters, its efficiency is calculated, and experiments with a 500 W prototype are conducted.

A Reduced Switch Count Seven-Level Boost ANPC Based Grid Following Inverter Topology With Photovoltaic Integration

A boost active-neutral-point-clamped (BANPC) multilevel inverter based on a switched-capacitor network generally shows a bargain between the number of switches and its voltage rating. Moreover, control complexities are increased with the increase in switch count. In this paper, a new single-phase seven-level boosted ANPC (7L-BANPC) topology using 8(eight) switches, one floating capacitor, and one dc source is presented. The proposed inverter is capable of producing 1.5 times voltage boosting and needs a lower switch voltage rating. The efficiency of the proposed inverter is increased significantly due to lower rating switching devices and a reduced number of total conducting switches. The unipolar level-shifted sine pulse width modulation is considered for controlling the proposed inverter. A three-phase single-stage grid-connected SPV system with the proposed 7L-BANPC inverter is implemented. For the proposed system, theoretical analysis and design calculations are illustrated. The steady-state and dynamic performances of the proposed inverter as well as the grid-connected SPV system under different load power factors, modulation indices, and environmental conditions are simulated using the MATLAB/Simulink software and tested using OPAL-RT real-time emulator. A comparison with existing topologies clearly shows the benefits of the proposed inverter.

Design and implementation of single switch integrated boost and flyback converter for renewable and sustainable energy.

Renewable resources are being explored to meet the increasing energy demand in the world. The development of RES and their integration into the grid necessitate a voltage conversion to match with the grid voltage. This conversion can be implemented using DC-DC converters. A high-gain DC-DC Converter with low loss is proposed in this article. Thus, the proposed integrated converter is obtained by incorporating a boost converter at the primary side of the flyback converter (FLC) and a VM cell at the secondary side to perform a elevated voltage gain at a lower duty ratio. The Switched Capacitor network is implemented to elevate the voltage gain. The dynamic performance of a controller can be enhanced using an FOPID controller. A comparison analysis has been done using the most recent topologies in order to confirm the superiority of the Proposed converter. A 100W experimental prototype model has been constructed in order to further validate the simulation results. The efficiency of this converter is demonstrably significantly higher than the current topology, according to measured performance. Therefore, it can be said that this topology can be used for applications involving renewable and sustainable energy.

Retuning high Q inductive power transfer systems at MHz frequencies: a switched capacitor design method incorporatingCOSS

AbstractHigh Q coils are required by inductive power transfer (IPT) links to attain reasonable levels of power transfer especially for loosely coupled links such as those used for small, deeply implanted medical devices. However, the high Q feature makes IPT systems strongly dependent on operating frequency which must be matched in the primary and secondary resonant tanks. Consequently, power transfer is sensitive to resonant frequency shifts due to component aging and environmental factors. Here, a switched capacitor (SC) network is developed to maintain tight matching and enhance system robustness. The combination of high voltage and high frequency required to achieve power transfer to deeply implanted devices makes the SC network design challenging. High frequencies require small tuning capacitance and high voltage requires MOSFETS with large output capacitance (COSS) resulting inCOSShaving a significant effect on tuning frequency. This paper proposes a parameter design method incorporatingCOSSto eliminate the uncertainty of voltage relatedCOSS. In the experiment, the SC network broadens the effective bandwidth from 37 to 585 kHz at the centre frequency of 6.50 MHz. Across a frequency sweep, the worst case in transfer power drop is −0.43 dB, which demonstrates sufficient immunity to parameter deviations.

Decoupled control of a high step-up multi-input converter for renewable energy applications

This paper focuses on the development and control of a non-isolated high step-up multi-input dc–dc converter for renewable energy applications. The converter has non-pulsed input currents and high voltage gain owing to the input inductors and a switched-capacitor (SC) network. In a two-input case, there are only two low-side switches controlled independently for adjusting individual input power levels and another low-side switch for operating the SC network. Steady-state analysis and dynamic modelling of the converter are provided. Design procedures regarding the hardware and decoupled control system dealing with the interactions of the control loops are given. After a benchmark study, a laboratory prototype rated at 200-W validates the analysis and tests the control system when subjected to step changes.

A 0.0022 mm² 10 bit 20 MS/s SAR ADC With Passive Single-Ended-to-Differential-Converter

This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC, such that it can convert single-ended input signals. As the SDC is passive, the overall solution is power-efficient compared to active SDC solutions, and is especially suitable for lower/medium resolutions. As opposed to active SDC solutions with a static bias current, the proposed switched-capacitor network only consumes dynamic power, such that its consumption scales linearly with the sampling frequency. This paper discusses the basic concept of the proposed scheme, and analyzes the impact of noise and other imperfections, describes the trade-offs for power and area, and discusses the consequences for the input driver. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$60~\mu \text{m}\,\,\times 36~\mu \text{m}$ </tex-math></inline-formula> .

A 320 μW Multi-Band Receiver with N-Path Switched-Capacitor Networks

This paper presents a multi-band ultra-low power (ULP) receiver with N-Path Switched-Capacitor (NPSC) networks in 90 nm CMOS process. The NPSC is integrated into the feedback loop of the low noise amplifier (LNA) to flexibly provide narrowband input matching at multiple sub-GHz Industrial, Scientific, and Medical (ISM) bands by adjusting the switching frequency. Moreover, the LNA with an NPSC network is utilized to suppress the out-of-band signal at the input and output of the LNA, simultaneously. In order to achieve an ultra-low power consumption, a sub-threshold LNA and four passive NPSC mixers are implemented in this receiver. The ULP receiver achieves a measured gain of 40±2 dB in ISM bands (430/860/915/960 MHz). The measured noise figure and out-of-band IIP3 are 10±0.5 dB and −0.3±2 dBm, respectively. The ULP receiver chip consumes 320 μW at 0.4 V power supply and occupies a chip area of 0.31 mm2.

A Dual-Branch Series-Parallel Hybrid Buck DC-DC Converter With Flying Capacitor Voltage Auto-Balancing

This paper presents a dual-branch series-parallel hybrid buck converter with flying capacitor voltage auto-balancing and reduced output impedance. The proposed converter automatically and inherently balances the flying capacitor voltages as one-third of the input voltage. Besides, the proposed converter operates in four states per cycle rather than the conventional six states, leading to a feasible Type-III compensation of the analog pulse-width modulation (PWM) controller. Moreover, due to the multiple parallel current paths in the switched-capacitor network, the proposed converter reduces the output impedance, thus decreasing the conduction loss. Finally, validated in 65-nm CMOS, the proposed converter regulates a 0.55 V–1 V output voltage from a 3.6 V input voltage over a large output power of 0.45 W with 82% peak efficiency, and switching frequency up to 5 MHz. It also automatically sets the flying capacitor voltages at 1.2 V.

A Novel Switched Capacitor Precharging Method for Three-Phase Induction Motor Drive Applications Utilizing the Winding Inductance

Three-phase (3-φ) induction motor drives operated with switched capacitor (SC) inverter circuits offer superior harmonic performance and voltage boosting. The SC network, however, generally requires additional circuitry to precharge the capacitor(s) to prevent inrush current. To obviate the requirement of the extra circuit, an innovative SC precharging scheme is presented, which utilizes the winding inductance of the motor. The inverter circuit is so operated that the motor winding inductance first stores electrical energy from the input dc source and then releases it to the SC. These two actions are continued till the SC is precharged to a voltage equal to the magnitude of the input dc source. The circuit operation during the precharging is similar to the operation of a conventional buck-boost type dc–dc converter. The precharging action is so designed that the voltage of the SC cannot increase further. Therefore, the proposed scheme does not need any voltage sensor. The operation of the circuit during precharging is analyzed extensively to develop a mathematical background for the given method. It is shown that by manipulating the switching frequency during the precharging the precharging time can be controlled as per the user requirements. Various claims are validated using computer simulations and experiments. All the results are presented.

An improved seven-level switched-capacitor-based neutral-point clamped inverter

Multilevel inverters (MLIs) have seen significant growth in a variety of medium- to high-power industrial applications and have become a mature and viable solution for renewable energy systems over the past decade. The major concerns of MLIs are the high component count and the buck-type feature of the ac output voltage when used for grid-connected renewable-energy-based sources such as solar photovoltaic (PV) panels. As another option, a switched-capacitor (SC)-based inverter possessing the feature of boost ability is a prime solution to meet the requirements of ac power applications. Integrating an SC network with a neutral-point clamped (NPC) structure makes leakage current alleviation viable for transformerless PV grid-connected systems. In this article, an improved SCMLI based on the NPC structure is proposed to reduce the number of active switches and the number of switches in the charging loop, significantly reducing the power loss. It can generate seven voltage levels with voltage boosting and self-balancing of capacitors within a single-stage power conversion. The working principle of the proposed topology, circuit description, and control technique are presented. Further, the proposed inverter was compared with other recent SC topologies to show its superiority. In the end, a laboratory prototype was developed and tested for the seven-level module under steady-state and dynamic conditions to validate the practical viability of the proposed configuration. The proposed inverter’s maximum efficiency was 97.5% at 1.2 kW rated power.

A high step-up non-isolated DC-DC converter with active switched-inductor and switched-capacitor networks

ABSTRACT This article proposes an enhanced non-isolated high-gain DC-DC converter for interfacing renewable energy sources (RESs). This converter utilizes active switched-inductor (ASL) and switched-capacitor (SC) networks in which the ASL network increases the voltage gain. Furthermore, using the SC network as a multiplier cell helps to reach a high voltage conversion ratio with a proper duty cycle. The main advantages of the proposed converter are the high voltage gain, continuous input current, and low voltage stress on the semiconductor switch and the passive component. Since the voltage stress of the semiconductor element is low, a low ON-state resistance switch is used, which leads to reduced conduction losses. Comprehensive analysis of the steady-state operation in continuous conduction mode (CCM), inductor and capacitor design, and a comparison considering other similar topologies are presented in this article. Also, the parasitic elements are assumed to calculate the DC-Voltage gain and the efficiency of the converter. Finally, simulation results are presented in the PSIM environment to validate the feasibility of the proposed converter.

Switched-Capacitor Bandgap Voltage Reference for IoT Applications

This paper presents a switched-capacitor network (SCN) based bandgap voltage reference (BGR) for IoT applications. The proposed BGR employs a dual proportional-to-absolute-temperature (PTAT) clock topology to achieve both high precision and low power over a wide temperature range while relaxing the capacitor size requirements. Specifically, the fast PTAT clock assists in reducing the output voltage ripple of the dual-branch interleaved <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> charge pump (CP). Meanwhile, the slow PTAT clock controls the voltage divider SCN to relax the settling error at low temperature and the leakage-induced error at high temperature simultaneously, resulting in lower power consumption and smaller temperature coefficient (TC). We also propose a replica <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {EB}}$ </tex-math></inline-formula> generation branch in the series-parallel SCN to improve the BGR output TC due to the finite settling time during switching. Fabricated in 65nm standard CMOS, measurement results show that the proposed BGR obtains a TC of 32 ppm/&#x00B0;C at 0.5V supply within &#x2212;40 &#x00B0;C to 120 &#x00B0;C. The line regulation is 3.3mV/V or 0.66&#x0025;/V from 0.5V to 1V. Based on 10-chip measurement results, we obtain a <inline-formula> <tex-math notation="LaTeX">$3\sigma / \mu $ </tex-math></inline-formula> variation of 1.37&#x0025; before trimming, while 0.25&#x0025; after applying one-point trimming at 20&#x00B0;C.

Novel Interleaved High Gain Boost Converter Using Switched Capacitor

The increase in global energy demand has led to increased research in harvesting solar energy. Solar energy is widely used in homes, electric vehicles and is a great solution to power remote areas. DC–DC converters are essential in extracting power from solar panels. One of the main problems in designing converters for solar energy applications is boosting the low output voltage of the solar panel to meaningful levels. While there are several topologies to achieve high gain, some of the problems faced by them are the extreme duty ratio, complex design and discontinuous input current. This paper presents a novel topology that uses an interleaved input, a voltage lift capacitor and a hybrid switched capacitor network to achieve high gain without an extreme duty ratio or bulky magnetics. The proposed converter is controlled using a microcontroller which regulates the output voltage. The voltage lift capacitor and the switched capacitor network enhances the voltage gain over a conventional boost converter without an extreme duty ratio. The analysis and design of the proposed converter are presented and verified with a 100 W prototype. The results show that the converter provides a gain of 10, at a duty ratio of 30%, while delivering the designed output power with considerably high efficiency.

Analysis of Dual-Inductor Hybrid Converters for Extreme Conversion Ratios

This article presents a dual-inductor hybrid (DIH) converter that is capable of efficient nonisolated dc–dc conversions with extremely large voltage conversion ratios. The converter topology combines a switched-capacitor network and two interleaved inductors, which supports simple duty-cycle control for output regulation. In order to achieve complete soft charging for all flying capacitors, a method to optimally size the capacitors has been proposed and verified. Detailed analysis of the two inductor currents revealing a new and simple method to modulate them and its impacts on output regulation and efficiency are also provided and demonstrated in experiments. Employing the converter topology and design methods, a DIH converter prototype is implemented and measured for a wide range of operating voltages, providing a 1–2-V output from a 48-V input and a 1–5-V output from a 150-V input with output currents up to 20 A. The converter achieves 94.3% peak efficiency at 48 V-to-2 V/7 A conversion and 93.7% at 150 V-to-5 V/18 A conversion.

Topology, Modeling and Control Scheme for a new Seven-Level Inverter With Reduced DC-Link Voltage

This paper presents a novel single-source three-phase multilevel converter with voltage boosting capability for medium-voltage photovoltaic applications. This converter consists of different switched-capacitor networks, formed by 1 capacitor and 3 active switches, as a basic switching cell to generate variable dc-link voltage that boosts the input dc-source voltage, producing 2n+1 (n2) voltage levels at the output. It can reduce the dc-link voltage requirements by 50% in comparison to the traditional neutral point clamped (NPC), flying capacitors, active NPC (ANPC), hybrid and hybrid clamped ANPC and cascaded H-bridge topologies, and 75% to advanced ANPC topologies. It can also reduce the number of required switches and capacitors as well as their voltage stresses compared to these state-of-the-art topologies reported in the literature so far. A finite control set model predictive control algorithm is derived to control the converter, which has the capability to control the active and reactive power without distorting the generated grid current quality. The capacitor voltage balancing is inherent in the proposed topology, and thus, there is no need for any additional voltage balancing circuit, which reduces the control complexity. As an example, a 7-level version of the proposed topology is compared to other existing 7-level inverter topologies.

An Improved Comparator Based on Current Reuse and a New Frequency Compensation Technique used in an OTA for Pipeline ADCs

In this paper, a comparator and an operational amplifier considered as essential components, constituting a 10-bit 50-MHz pipeline Analog-to-Digital Converter for Wireless Local Area Network (WLAN) applications, are described and designed. All post-layout and Monte-Carlo simulations, using a 0.35[Formula: see text][Formula: see text]m CMOS AMS process technology with [Formula: see text][Formula: see text]V supply voltage and an input common-mode range of [Formula: see text][Formula: see text]V, are achieved. An improved clocked comparator with a dynamic latch, based on a switched capacitor network, using the current reuse technique for slew rate enhancement and positive feedback for offset voltage compensation, is presented. The operational amplifier, consisting of a fully differential folded cascode operational transconductance amplifier, providing high-gain and good stability, is exhibited. A new frequency compensation technique, based on active resistors, is used to improve amplifier phase-margin. The Monte-Carlo performance results of the designed clocked comparator provide an offset voltage of [Formula: see text][Formula: see text]mV with [Formula: see text][Formula: see text]mV 3[Formula: see text] deviation, a slew rate of [Formula: see text]V/ns with [Formula: see text]V/ns 3[Formula: see text] deviation, and a propagation delay of [Formula: see text][Formula: see text]ns with [Formula: see text][Formula: see text]ns 3[Formula: see text] deviation. Monte-Carlo performance results of the designed operational amplifier provide a phase-margin of [Formula: see text], and a high-gain of [Formula: see text]dB with [Formula: see text] and [Formula: see text]dB 3[Formula: see text], respectively, by using [Formula: see text] load capacitance.