Switching Power Consumption Research Articles

Design of Micro-ring Resonator Based 4 × 4 Optical Router for Photonic Network Applications

A 4 × 4 optical router which is composed of only four micro-ring resonator based switching elements is designed without any need of optoelectronic conversion for use in integrated optical networks. The geometrical structure including the number of rings and waveguide junctions are optimized through numerical simulation, which minimizes the crosstalk and the transmission loss and improves the loss of different paths of the optical router. The design can route four optical single-wavelength input signals to any of the four output ports and provided extinction ratio larger than 14 dB for all available optical paths. The average switching power consumption is about 1.2 mW per ring. The routing functionality and optical signal reliability are confirmed through numerical simulation.

Benchmarking of Spin–Orbit Torque Switching Efficiency in Pt Alloys

AbstractA magnetic heterostructure with good thermal stability, large damping‐like spin–obit torque (DL‐SOT), and low power consumption is crucial to realize thermally stable, fast, and efficient magnetization manipulation in SOT devices. This work systematically investigates on PtxCu1‐x/Co/MgO magnetic heterostructures with perpendicular magnetic anisotropy (PMA), and reports a promising spin Hall material, Pt–Cu alloy, possessing large DL‐SOT efficiency and moderate resistivity. The optimal Pt0.57Cu0.43 has a large DL‐SOT efficiency of about 0.44, as determined by hysteresis loop shift measurements, with a relatively low resistivity (82.5 µΩ cm at 5 nm thickness). Moreover, this large DL‐SOT efficiency and the coercivity reduction accompanying with proper alloying contribute to a low critical switching current density (2.37 × 106 A cm−2 in the Pt0.57Cu0.43 layer) in current‐induced magnetization switching measurements. Finally, the thermal stability of the Co layer can be preserved under alloying, whereas the switching power consumption can be significantly reduced, being the best performance among reported Pt‐based spin current sources. This systematic study on SOT switching properties suggests that Pt0.57Cu0.43 is an attractive spin current source with moderate resistivity, large DL‐SOT efficiency, good thermal stability, and low power consumption for future SOT applications.

Semi-Automated Extraction of the Distribution of Single Defects for nMOS Transistors.

Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is typically beneficial for their operating characteristics, such as switching speed and power consumption, but at the same time miniaturization also leads to increased variability among nominally identical devices. Adverse effects due to oxide traps in particular become a serious issue for device performance and reliability. While the average number of defects per device is lower for scaled devices, the impact of the oxide defects is significantly more pronounced than in large area transistors. This combination enables the investigation of charge transitions of single defects. In this study, we perform random telegraph noise (RTN) measurements on about 300 devices to statistically characterize oxide defects in a Si/SiO technology. To extract the noise parameters from the measurements, we make use of the Canny edge detector. From the data, we obtain distributions of the step heights of defects, i.e., their impact on the threshold voltage of the devices. Detailed measurements of a subset of the defects further allow us to extract their vertical position in the oxide and their trap level using both analytical estimations and full numerical simulations. Contrary to published literature data, we observe a bimodal distribution of step heights, while the extracted distribution of trap levels agrees well with recent studies.

A 99.79% energy saving switching scheme without third reference level and reset energy for SAR ADC

An energy-efficient capacitor switching scheme is proposed for successive approximation register analog-to-digital converter. During the design process, the semi-resting DAC structure and charge characteristic of floating capacitor ensure significant energy saving. There is no switching power consumption in the first two comparison process. Compared with the conventional switching scheme, the proposed method decreases 99.79% switching energy and 73.8% capacitor area. Benefit from merge-and-split method, only two reference levels are utilized in this novel scheme, where the power and accuracy of generating the third reference voltage are not necessary to consider. Besides, the reset energy of the proposed scheme is verified to be 0. Furthermore, the common mode voltage at comparator inputs is kept at 0.5Vref except merely a 0.5LSB reduction due to LSB-down technique.

Spin‐Orbit Torque Driven Magnetization Switching and Precession by Manipulating Thickness of CoFeB/W Heterostructures

AbstractThe switching of magnetization via spin‐orbit torque has attracted much attention because of its fast switching and low power consumption. Numerous studies have focused on increasing the conversion efficiency from charge to spin current and out‐of‐plane magnetization cases. Recently, there have been reports on the fast and deterministic switching of in‐plane magnetization devices. It is reported that an in‐plane spin‐orbit torque (SOT) device can archive the oscillation, precession, and direct switching by a combination of torques—controlling the thickness of the ferromagnet and normal metal. With proper layer thicknesses, the device can show the three dynamics listed above at each current density in a macro spin simulation. Based on an understanding of the role of torque‐driving magnetization dynamics, a dynamic map of an in‐plane SOT device depending on torque efficiency and current density is shown.

Silicon Non-Blocking 4 × 4 Optical Switch Chip Integrated With Both Thermal and Electro-Optic Tuners

We experimentally demonstrate an integrated strictly non-blocking silicon 4 × 4 optical switch chip that can be operated in both thermo-optic (TO) and electro-optic (EO) switching modes. It is based on the double-layer network (DLN) architecture and consists of twelve 2 × 2 Mach-Zehnder interferometer (MZI) switch elements. TO phase shifters based on TiN microheaters and EO phase shifters based on p-i-n diodes are embedded in both waveguide arms of the MZI elements. The power consumption for TO and EO switching is 34 mW/π and 7 mW/π, respectively. The on-chip insertion losses are 1.74 ± 0.59 dB and 3.79 dB ± 1.32 dB for TO and EO switching, respectively. Due to the merits of the DLN architecture and the optimized performance of the switch elements, the chip possesses low crosstalk of -29.1 dB and -19.4 dB for TO and EO switching, respectively. Quadrature phase-shift keying (QPSK) optical signals with a data rate of 64 Gb/s are transmitted through the switch with no observable deteriorations. Such an optical switch is a promising candidate for both optical circuit switching and optical packet switching for a variety of applications.

A buck converter based on dual mode asynchronous pulse width modulator

This paper presents a buck type DC-DC converter based on an asynchronous pulse width modulator (APWM). The proposed APWM is a self-oscillating circuitry which is composed of a binary comparator (BAPWM) and a distinctive digitally controlled delay cell. The oscillating frequency of the BAPWM can be tuned by the delay of the modulator loop. By increasing the delay of the modulator loop, the switching frequency decreases and the BAPWM can be reconfigured as a low frequency APWM (LFAPWM) modulator to meet the efficiency requirement at light loads. Also, to save the switching power consumption the high-side power switch size is scaled according to the load conditions. Since the carrier signal is internally generated by the APWM itself, there is no major concern about the ramp signal discontinuity which is make duty cycle disturbance. In addition to, from the point of view of the output spectrum, the proposed converter provides a better performance compared to the conventional PWM (CPWM) and PFM due to its noise shaping property. The proposed converter is designed and simulated in a 0.13-µm CMOS technology to convert an input voltage of 5 V to the output voltage of 2.5 V with the maximum load current of 1 A. The conversion efficiency with full loading range for the 2.5 V output voltage is higher than 85% whereas the peak efficiency is about 92%.

Effects of device structure on thermo-optic switch and design optimization

The study on reliability of multi-layer structure of thermo-optic switch under thermal mechanical coupling effect is the basic research subject in modern micro-optoelectronics. Power consumption and response time are the most important performance indexes. Based on the generalized thermoelasticity theory, thermo-optic switch models of various structures are built to simulate the temperature and stress field for structure optimization. The numerical results show that an appropriate cross-section shape can reduce the switch power consumption without prejudice to the response speed, the refractive index of the core layer varies with the temperature, and the inter-layer thermal mismatching stress of the double-ridge structure is the maximum. The above findings will introduce new ideas for research and development and design of new optic switches.

A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier

This brief presents an ultra-low-power two-channel 12b 140 MS/s 28-nm CMOS analog-to-digital converter (ADC) for use in next-generation mobile communications systems. The proposed ADC employs a two-stage pipelined successive-approximation register (SAR) ADC architecture, where the SAR ADC at each stage determines 5b and 8b, respectively. In the first-stage 5b SAR ADC, the switching power consumption is significantly reduced due to the switching operation by only a separate digital-to-analog converter (DAC) with a small unit capacitance, which generates the comparator decision threshold. When this setup is applied to an actual system, the reference voltage driver of the system is less burdened. Furthermore, the SAR ADC employs a custom-encapsulated capacitor to improve the limited linearity of a DAC caused by parasitic capacitance. A residue amplifier employs an ultra-low power ring amplifier structure. The amplifier is shared by each channel to reduce not only the power consumption and die area but also channel mismatches. The prototype ADC in a 28-nm CMOS process demonstrates a measured differential non-linearity and integral non-linearity within 1.50 LSB and 2.85 LSB at 12b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 58.0 dB and 73.7 dB at 140 MS/s, respectively. The ADC occupies an active die area of 0.202 mm2 and consumes 1.1 mW at a 0.8-V supply voltage, corresponding to a figure of merit of 12.1 fJ/conversion-step.

Design of a 2 × 4 Hybrid MMI-MZI Configuration with MMI Phase-Shifters.

This paper reports design of a 2 × 4 hybrid multimode interferometer-Mach-zehnder interferometer (MMI-MZI) configuration consiting of compact thermo-optical switches on the silicon-on-insulator (SOI) platform. The device consists of two identical MMI slab waveguides as power splitters and couplers that are connected with two identical MMI-based phase shifters, and linear tapers at both ends of the MMIs to minimize the power coupling loss. A thin Al pad is used as a heating element and a trench is created around this pad to prevent heat from spreading, and to minimize loss. The calculated average thermo-optical switching power consumption, excess loss, and power imbalance are 1.4 mW, 0.9 dB, and 0.1 dB, respectively. The overall footprint of the device is 6 × 304 . The new heating method has advantages of compact size, ease of fabrication on SOI platform with the current CMOS technology, and offers low excess loss and power consumption as demanded by devices based on SOI technology. The device can act as two independent optical switches in one device.

Design and comparative analysis of D-Flip-flop using conditional pass transistor logic for high-performance with low-power systems

Flip-flop is one of the essential elements of data path structure design in the digital era. In this paper, the peculiar Flip-flop topologies, called as Conditional Pass Logic Static D-Flip-Flop (CPLSDFF) and Conditional Pass Logic Dynamic D-Flip-Flop (CPLDDFF) are proposed. The main objective of the proposed system is to optimize the primary performance criterions such as area and power. The first parameter is attained by reducing the device count, and the later is achieved by removing the redundant transistor switching, charge sharing and frequent power consumption from the source. The CPLSDFF and CPLDDFF are designed using SPICE with 130 nm IBM transistor technology and it shows that the silicon area is reduced up to 27% and 22% respectively. The conditional pass-transistor logic method is introduced in the proposed system leads to minimizing the unnecessary switching activity, charge sharing in intermediate nodes and power utilization is also minimized up to 12% in the static model, 70% in the dynamic model. The various performance parameters like transistor count, the clock driving power, data driving power, switching activity and propagation delay (D-Q) of the Flip-flop are investigated in detail and are correlated with the existing designs. The optimized CPLFF structures are also employed in 8-bit serial in serial out (SISO) shift registers and can save power up to 35% and 42% respectively. The outcomes show that the proposed system is most adaptable for low power applications with superior performance in register designs.

Improved low power implicit pulse triggered flip-flop with reduced power dissipation

In this paper, an improved implicit pulse triggered flip-flop is proposed based on conditional pulse enhancement scheme. The pass transistor logic AND gate creates a faster discharge path. Then a conditional pulse enhancement scheme is used in order to conditionally enhance the pulse only when required. This avoids unnecessary switching action in the flip-flop. Then in order to reduce the power dissipation further, the pseudo NMOS logic is replaced with a NAND gate structure. This reduces the static power consumption and as well as the switching power consumption. Thus results in an overall power saving. The results are obtained in 180 nm CMOS technology using mentor graphics. The results are compared with four conventional flip-flops and its power saving is improved.

Nonvolatile and ultra-low-loss reconfigurable mode (De)multiplexer/switch using triple-waveguide coupler with Ge2Sb2Se4Te1 phase change material

Mode-division multiplexing (MDM) is a promising approach to dramatically enhance the transmission capacity. A reconfigurable mode (De)multiplexer/switch (RMDS) is a key component for the flexible mode routing in the MDM network. A nonvolatile and ultra-low-loss RMDS is proposed via a triple-silicon-waveguide directional coupler with the Ge2Sb2Se4Te1 (GSST) phase change material (PCM). The nonvolatile property of GSST makes it attractive to reduce the switching power-consumption. Benefiting from the low loss of the GSST-PCM at both amorphous and crystalline states, an RMDS with an ultra-low loss and a high extinction-ratio can be realized. The proposed RMDS is optimally designed by using the full-vectorial finite element method and 3D full-vectorial finite difference time domain method. The numerically simulated results show that a compact RMDS is with the extinction ratios of 18.98 dB and 22.18 dB, ultra-low insertion losses of 0.10 dB and 0.68 dB for the “OFF” and “ON” states, respectively at the operating wavelength of 1550 nm. An ultra-wide bandwidth of 100 nm is achieved for both the “OFF” and “ON” states.

Very‐Low‐Temperature Integrated Complementary Graphene‐Barristor‐Based Inverter for Thin‐Film Transistor Applications

AbstractComplementary graphene‐barristor‐based inverters using n‐type ZnO:N and p‐type dinaphtho‐[2,3‐b:2′,3′‐f]thieno[3,2‐b]thiophene semiconductor layers are fabricated at a maximum process temperature lower than 200 °C. The devices display on/off ratios greater than 104. The transmittance of the device stack is higher than 80% at wavelengths larger than 470 nm. The complementary graphene‐barristor inverter exhibits a high gain (>8 at VDD = 2 V) by using a back‐gate structure, which allows for aggressive gate‐dielectric scaling. The potential performance of the inverter, as projected using experimental device parameters, shows that a very high voltage gain of over 70 and a low switching power consumption of below 10 nW can be achieved at VDD = 2 V and an equivalent oxide thickness of 1 nm. These performances are very promising for thin‐film transistor applications.

A New Power Gating Circuit Design Approach Using Double-Gate FDSOI

Power gating circuits are utilized to manage power consumption and thermal stress in microprocessors and other high-performance integrated circuits. Most of the power gating techniques utilize sleep transistors in different configurations to reduce the subthreshold leakage current, which is the primary source of the standby power. These sleep transistors, which are added between the supply lines and the circuits as header and footer switches, impose additional area, delay, power, and other overheads and complexities. This brief introduces the concept of combining the functionality of the sleep transistors with the logic devices by utilizing fully depleted silicon-on-insulator (FDSOI) device. This FDSOI transistor-based power gating circuit design approach will eliminate the requirement of employing a separate set of sleep transistors to place the circuit in the sleep or idle mode. This will reduce the overall complexity and overheads of integrated circuits and simplify power gating techniques. In addition, it improves the overall power efficiency and lower thermal effects. SOI devices are becoming critically important for various very-large-scale integration applications, because SOI devices provide higher performance and reliability, and options to design circuits with multiple-threshold voltages to ensure faster switching and lower power consumption. In the proposed circuit design approach, the flexibility to control the threshold voltage of a double-gate FDSOI device via back gate has been exploited to eliminate the need for using a separate set of sleep transistors. The presented sleep transistor design is verified via HSPICE simulation using the Leti-UTSOI model from CEA-Leti .

Photonic switching in high performance datacenters [Invited

Photonic switches are increasingly considered for insertion in high performance datacenter architectures to meet the growing performance demands of interconnection networks. We provide an overview of photonic switching technologies and develop an evaluation methodology for assessing their potential impact on datacenter performance. We begin with a review of three categories of optical switches, namely, free-space switches, III-V integrated switches and silicon integrated switches. The state-of-the-art of MEMS, LCOS, SOA, MZI and MRR switching technologies are covered, together with insights on their performance limitations and scalability considerations. The performance metrics that are required for optical switches to truly emerge in datacenters are discussed and summarized, with special focus on the switching time, cost, power consumption, scalability and optical power penalty. Furthermore, the Pareto front of the switch metric space is analyzed. Finally, we propose a hybrid integrated switch fabric design using the III-V/Si wafer bonding technique and investigate its potential impact on realizing reduced cost and power penalty.

Low-Power Capacitor-Splitting DAC with Mixed Switching Schemes for SAR ADCs

A low-power capacitor-splitting digital-to-analogue converter (DAC) for successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. During the first three bit cycles, with proper switching, there is no average switching power consumption. From the fourth bit cycle, one-side double-level switching scheme or the monotonic one is utilized based on the first two bits. When the first two bits are the same, one-side double-level switching scheme is chosen. Otherwise, the monotonic one is adopted. Thus, the proposed switching method only requires 5.27 CV[Formula: see text] average switching energy, 75.29% less compared to the Sanyal and Sun proposed one.

Improved low power implicit pulse triggered flip-flop with reduced power dissipation

In this paper, an improved implicit pulse triggered flip-flop is proposed based on conditional pulse enhancement scheme. The pass transistor logic AND gate creates a faster discharge path. Then a conditional pulse enhancement scheme is used in order to conditionally enhance the pulse only when required. This avoids unnecessary switching action in the flip-flop. Then in order to reduce the power dissipation further, the pseudo NMOS logic is replaced with a NAND gate structure. This reduces the static power consumption and as well as the switching power consumption. Thus results in an overall power saving. The results are obtained in 180 nm CMOS technology using mentor graphics. The results are compared with four conventional flip-flops and its power saving is improved.

Lightpath Management in SDN-Based Elastic Optical Networks With Power Consumption Considerations

Elastic optical networks (EONs) are increasingly used to interconnect data centers. As interdatacenter traffic is expected to continue to grow at high rates for the foreseeable future, it becomes imperative to address the respective growth in power consumption within EONs. In this paper, we take the first steps toward enhancing the energy efficiency of interdatacenter EONs. Specifically, we use traffic prediction techniques for centralized lightpath management that leverages the capabilities of software defined networking (SDN) technology. Our objective is to eliminate unnecessary lightpath termination and re-establishment operations, and in turn decrease switching power consumption within the network. Our evaluation study confirms that the proposed algorithm is effective in achieving substantial savings in power consumption while maintaining a bandwidth blocking ratio at levels comparable to those of earlier algorithms.

High-Performance Single-Active-Layer Memristor Based on an Ultrananocrystalline Oxygen-Deficient TiOx Film.

The theoretical and practical realization of memristive devices has been hailed as the next step for nonvolatile memories, low-power remote sensing, and adaptive intelligent prototypes for neuromorphic and biological systems. However, the active materials of currently available memristors need to undergo an often destructive high-bias electroforming process in order to activate resistive switching. This limits their device performance in switching speed, endurance/retention, and power consumption upon high-density integration, due to excessive Joule heating. By employing a nanocrystalline oxygen-deficient TiOx switching matrix to localize the electric field at discrete locations, it is possible to resolve the Joule heating problem by reducing the need for electroforming at high bias. With a Pt/TiOx/Pt stacking architecture, our device follows an electric field driven, vacancy-modulated interface-type switching that is sensitive to the junction size. By scaling down the junction size, the SET voltage and output current can be reduced, and a SET voltage as low as +0.59 V can be obtained for a 5 × 5 μm2 junction size. Along with its potentially fast switching (over 105 cycles with a 100 μs voltage pulse) and high retention (over 105 s) performance, memristors based on these disordered oxygen-deficient TiOx films promise viable building blocks for next-generation nonvolatile memories and other logic circuit systems.