Switch-level Fault Research Articles

Analysis of reliability for fault tolerant design in NANO CMOS logic circuit

The emerging nano scaled electronic devices are Carbon Nanotubes (CNT), Silicon nanowires (SINW), nano CMOS switches etc. In Nano CMOS switches, the devices can be interconnected to build the nano scaled CMOS circuit. In this nano CMOS circuit, faults occur at three levels, such as gate level, circuit level and switch level. This paper focusses on the switch level faults of stuck-open or stuck-off and stuck-short or stuck-on that frequently occurs in CMOS switches. To overcome the switch level faults and to increase the reliability, the fault tolerant technique known as the Quadded Transistor (QT) structure is used. An analytical model has been formulated to determine the probability of failure by analyzing the stuck open and stuck short faults. Also, the model has been formulated by implementing QT structure for the single CMOS NAND2 gate. By the use of analytical formulations, the results has been simulated for the occurrence of minimum to maximum number of defective transistors in CMOS logic circuit.

FPGA-based switch-level fault emulation using module-based dynamic partial reconfiguration

In order to design a fault tolerant digital system, it is necessary to understand its behavior with the presence of faults in early design stage. Fault simulation is a process to purposely inject faults into a software circuit model and observe its faulty behavior. However, such simulation’s runtime tends to grow exponentially when test circuit becomes large. FPGA-based fault emulation, which is fault simulation implemented in FPGA, is an efficient way to accelerate fault simulation process. This paper introduces a novel FPGA-based switch-level fault emulation system utilizing module-based dynamic partial reconfiguration. In this approach, faults are modeled at switch-level and mapped to gate-level description for efficient FPGA implementation. The circuit under test is partitioned using unbalanced partitioning structure so that faults are injected only in a small sub-circuit. Using module-based dynamic partial reconfiguration, faulty circuit partition can be downloaded to FPGA without erasing the fault-free part of the circuit. The resulting system’s runtime increases linearly with circuit size, therefore indicating high efficiency of this system when emulating large and complex circuits.

A novel scheme to improve fault-tolerant capabilities of multistage interconnection networks

In this paper, we propose a novel augmenting and partitioning scheme for constructing multistage interconnection networks (MINs) with improved fault-tolerant capabilities. We first propose a partitioning scheme to construct and analyze partitioned MINs (PMINs). A simulation method is developed, based on the stuck-at fault model, to evaluate dynamic full access (DFA) and average number of passes in PMINs. We then propose an augmenting scheme to construct augmented partitioned MINs (APMINs) with further enhanced fault-tolerant capabilities. Simulation analysis of APMINs, based on the switch level fault model, showed that the proposed scheme significantly improves the fault-tolerant capability of MINs. Finally, the effectiveness of the proposed scheme is evaluated with respect to cost, DFA, locality, and average path length.

FX: a fast approximate fault simulator for the switch-level using VHDL

Switch-level faults, as opposed to traditional gate-level faults, can more accurately model physical failures found in an integrated circuit. However, one problem with switch-level fault simulation is that of long simulation times. This paper addresses this problem by performing fast approximate switch-level fault simulation using transistor reverse level ordering, and a novel nine-valued switch-level extension to observability. The probability of propagation of a fault from an arbitrary line of the switch-level circuit to the primary output is shown to be a function of the average node fan-in and the line's distance to primary output. Using this probability, results show one order of magnitude of complexity speed-up as compared to traditional fault simulation techniques, while maintaining good accuracy.

Switch-level Differential Fault Simulation of MOS VLSI Circuits

A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. Every compiled circuit component is assigned a dominance attribute, which abstracts relative strength information in the circuit. Dominance is used during simulation to resolve the X-state due to fighting pull-up and pull-down transistor paths and also to deduce transistor fault detectability and fault equivalencies prior to simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level. Differential fault simulation provides excellent performance with minimum memory requirements, although it incurs a higher overhead at the switch-level than at the gate-level due to the dynamic memory properties of MOS circuits.

Parallel Switch-Level Fault Simulation Performance Modeling using VHDL

Switch-level faults, as opposed to traditional gate-level faults, can more accurately model the physical failures found in the integrated circuit. However, existing fault simulation techniques have a worst-case computational complexity of O(n 2), where n is the number of devices in the circuit. A Parallel Hardware Accelerated Fault Simulator (PHAFS) has been proposed in order to reduce fault simulation complexity to O(L2), where L is the number of levels of switches encountered when traversing the circuit from output to input. This paper presents the VHSIC (Very High Speed Integrated Circuit) hardware description language simulation techniques used to verify the parallel fault simulation algorithm and to verify the algorithm's complexity. This paper also presents predicted speed-up performance results versus partition size for benchnark circuits.

Active timing multilevel fault-simulation with switch-level accuracy

This paper describes SATISFAULT, a new hierarchical multilevel fault simulator with switch-level fault models and switch-level accuracy. SATISFAULT's intelligent scheduling mechanism switches between the abstraction levels to force simulation at the highest, thus fastest, possible level of abstraction without losing switch-level accuracy. The simulation algorithm is based on single fault-propagation for active faults. It deals with multiple abstraction levels and supports the inertial delay model. As a result, even large circuits may be fault-simulated accurately with all faults injected at the switch-level. Complete fault-simulation of all transistors stuck-on and stuck-open of circuits up to 105000 transistors including faults inside flip-flops is possible in reasonable time. In addition, SATISFAULT is also capable of simulating bridging faults for IddQ detectability.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Performance analysis of augmented partitioned multistage interconnection networks

In previous work, a novel scheme for constructing fault-tolerant multistage interconnection networks (MINs) was presented. The constructed augmented partitioned MINs (APMINs) were evaluated using a switch level fault model in terms of full access (FA) and dynamic full access (DFA) measures. The simulation results showed that the proposed scheme significantly improved the fault-tolerant capability of MINs. Based on the small synchronous clock scheme, we first analyze the performance of this class of synchronous packet-switched APMINs. We then evaluate the performance of the APMIN-based tightly coupled and loosely coupled multiprocessor systems using a hybrid probabilistic and queueing model. The performance of this class of fault-tolerant multiprocessor systems and that of systems employing Omega and modified Omega (MD-Omega) networks are also compared.

Switch-level fault detection and diagnosis environment for MOS digital circuits using spectral techniques

A switch-level fault detection and diagnosis environment for MOS digital circuits using a compression data method based on a spectral signature is described. The selected fault model includes an MOS transistor permanently On and Off, breaks in internal gate lines, and shorts between two internal nodes of different logic gates, or between the internal nodes within the same complex gate. Circuit editing is performed in modules containing simple switch-level descriptions of the transistors. From the module structure a fault list is created, which will later be processed to eliminate all equivalent faults (fault collapsing). Simulation of the faults contained in this lift, and Walsh or Haar spectral analysis of the outputs, allow a data file to be created, containing a list of faults detected, a list of diagnosed fault groups and the spectral signature for each of these groups. The circuits are tested by comparing the information contained in this file and the data provided by a logic analysis system (LAS).< >

Fault simulation in CMOS VLSI circuits

In digital complementary metal-oxide semiconductor (CMOS) very large-scale integration (VLSI) circuits, physical faults, such as transistor stuck-closed, floating line faults and bridging faults (which include gate-to-drain shorts) cause complex analogue behaviour of the digital circuit. Some of these faults create an intermediate voltage level, which classical switch-level fault simulator techniques are unable to interpret. A general fault simulator is proposed which employs a new technique for evaluating the faulty subcircuit based on analysis of a nonlinear resistive circuit. The technique can be considered an extension of classical switch-level level fault simulators, in which most of the possible physical faults are considered. >

Switch-level testability of the dynamic CMOS PLA

Functional testing, as opposed to parametric testing, plays an important role in testing VLSI integrated circuits. However, it appears that designs are not always carefully analysed in advance to determine precisely which faults are clean, i.e. testable by logic means alone. The programmable logic array (PLA) is a popular circuit form used to implement a system of Boolean functions over a set of input variables. This paper considers the testability of the dynamic CMOS PLA with respect to an extended switch-level fault model that includes node faults, transistor stuck-opens and stuck-ons, interconnect breaks, ohmic shorts, and crosspoint faults. Single occurrences of each fault in the fault model are classified as either clean, unclean, or clean subject to conditions on the products and output functions computed by the PLA. Finally, a modified dynamic CMOS PLA design is described and its improved switch-level testability properties are given.

Design of large embedded CMOS PLAs for built-in self-test

A novel scheme to design built-in self-test programmable logic arrays (PLAs) implemented with CMOS technology is described, which is attractive for large arrays. These PLAs can perform function-independent self-test at normal operating speed, can detect CMOS switch-level faults, and have a lower area overhead than any other BIST scheme. A sequential parity checking technique is used to test for the AND and OR arrays of the PLA. This technique does not require any XOR cascade to evaluate parity data as in the parallel checking technique used by other schemes, thus achieving an order of magnitude reduction in total testing time. The method accounts for switch-level stuck-open and stuck-on faults in addition to conventional stuck-at, crosspoint, and bridging faults. A novel circuit design technique was used to implement the test pattern generator for product lines. It makes use of a Johnson counter and a two-level decoding network to obtain a very low area overhead and to match the pitch between the PLA and the test circuitry. >

Designing CMOS Circuits for Switch-Level Testability

Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level faults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. An inverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-on faults.