Fault simulation in CMOS VLSI circuits

Abstract

In digital complementary metal-oxide semiconductor (CMOS) very large-scale integration (VLSI) circuits, physical faults, such as transistor stuck-closed, floating line faults and bridging faults (which include gate-to-drain shorts) cause complex analogue behaviour of the digital circuit. Some of these faults create an intermediate voltage level, which classical switch-level fault simulator techniques are unable to interpret. A general fault simulator is proposed which employs a new technique for evaluating the faulty subcircuit based on analysis of a nonlinear resistive circuit. The technique can be considered an extension of classical switch-level level fault simulators, in which most of the possible physical faults are considered. >