Switch Driver Circuit Research Articles

An analog switch circuit structure suitable for low-distortion transmission

Abstract A MOSFET analog switch circuit structure suitable for low-distortion bidirectional signal transmission is proposed. By introducing a “threshold voltage matching MOSFET” into the MOSFET switch driver circuit structure, the driving voltage corrected by the threshold voltage is generated by the driving circuit, eliminating the problem of poor conduction on-resistance flatness in traditional analog switch circuit structure due to MOSFET second-order effects and non-constant overdrive voltage. The circuit completed schematic and layout design based on the 0.13 μm BCD process. Simulation results show that the switch has bidirectional transmission capability, with a typical on-resistance value of 115 Ω. It achieves less than 5% on-resistance non-flatness under resistive loads ranging from 500 Ω to 1 KΩ, which is more than 50% improvement compared to traditional analog switch structures. Moreover, the on-resistance flatness is insensitive to changes in load and temperature.

Reduced Switch Cascaded Multilevel Inverter With New Selective Harmonic Elimination Control for Standalone Renewable Energy System

Recently multilevel inverters (MLIs) have received wide attention from industry and academia, as they are changing into a viable technology for diverse applications. To produce high-quality output using less switch count, development of novel reduced switch MLI (RS MLI) topologies has been a focus of current research theme. This paper presents design and control of a switched-diode dual source single switch MLI (SDDS MLI). The generalized SDDS MLI is first designed using an asymmetric basic unit. Proposed SDDS MLI requires less switch count and driver circuit count compared with the few recently developed RS MLI topologies. To improve the voltage quality by eliminating targeted low-order harmonics, a modified version of fish swarm optimization algorithm is examined for computing optimum switching angles required to control the SDDS MLI. Moreover, suitability and superiority of the derived algorithm are established by comparing with traditional selective harmonic elimination techniques. The developed topology is investigated through several MATLAB simulations as well as experimental tests in the laboratory applying the modified control approach.

Single-Phase Active Power Harmonics Filter by Op-Amp Circuits and Power Electronics Devices

This paper introduces a new structure for single-phase Active Power Harmonics Filter (APHF) with the simple and low-cost controller to eliminate harmonics and its side effects on low voltage grid. The proposed APHF includes an accurate harmonic detector circuit, amplifier circuit to trap tiny harmonics, switching driver circuit for precise synchronization, and inverter to create injection current waveform, which is extracted from reference signal. The control circuits are based on electrostatic devices consist of Op-Amp circuits. Fast dynamic, simplicity, low cost, and small size are the main features of Op-Amp circuits that are used in the proposed topology. The aim is removing the all grid harmonic orders in which the proposed APF injects an appropriate current into the grid in parallel way. The proposed control system is smart enough to compensate all range of current harmonics. A prototype is implemented in the power electronics laboratory and it is installed as parallel on a distorted grid by the non-linear load (15 APeak-Peak) to verify the compensating of harmonics. The harmonics are compensated from THD% = 24.48 to THD% = 2.86 and the non-sinusoidal waveform is renovated to sinusoidal waveform by the proposed APHF. The experimental results show a good accurate and high-quality performance.

Integrated 0–30 V switching driver circuit fabricated by mesa isolation postprocess of standard 5 V CMOS LSI for MEMS actuator applications

A 30 V switching circuit with standard CMOS foundry-made transistors on a silicon-on-insulator (SOI) wafer is proposed.The key fabrication process is mesa isolation postprocessing that physically separates a series-connected transistor's body so that we can apply independent substrate (body) voltages to each transistor. The process is a combination of anisotropic and isotropic deep reactive ion etching (DRIE) with a single mask. In the experiment, CMOS transistors were fabricated on a 9-µm-thick 6-in. SOI wafer in an LSI foundry company, and the postprocess was carried out in a MEMS cleanroom. In this paper, full integration with gate-voltage-level shift circuits and dynamic driving of an electrostatic comb-drive MEMS device with series-connected transistors are presented.

Low‐power SOI CMOS antenna switch driver circuit with RF leakage suppression and fast switching time

A low-power antenna switch driver circuit with RF leakage suppression and fast switching time is implemented in a 0.25 μm silicon-on-insulator (SOI) CMOS process. It is composed of a three-stage current starved ring oscillator with a clock buffer, a charge pump and a latch-based three-state logic driver. The negative voltage from the charge pump is fed into the latch-based three-state logic driver, and it generates three states of logic level (+VDD, GND and −VDD) according to the decoder signal without any reliability issue. In addition, the proposed three-state logic driver with an optimal negative resistance value reduces the amount of the RF leakage coupling into the charge pump while maintaining its switching time fast. In the measurement, the designed switch driver circuit shows 30 dB of isolation over 100 MHz to 3 GHz frequency range.

Reduction in number of devices for symmetrical and asymmetrical multilevel inverters

Multilevel inverter (MLI) is receiving remarkable recognition due to its reduced voltage stress across the power switches and low total harmonic distortion in output voltage. However, MLI incorporates large number of semiconductor switches and hence increases its complexity. In this study, new structures of symmetrical and asymmetrical MLI are proposed. The proposed structures offer reduced number of controlled switches, power diodes, capacitors and DC sources as compared with classical and recently proposed topologies in the line. Reduction of switch count, driver circuit and DC voltage sources reduces the size, cost, complexity and enhances overall performance. Moreover significant reduction in voltage stress across the switches can be achieved. A comparative analysis of proposed topologies with the classical topology and recently published topologies has been made in terms of controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi-carrier pulse width modulation strategy is adopted for generating the switching pulses. The detailed simulation study of the proposed topology has been carried out using MATLAB/Simulink and feasibility of topology has been validated experimentally.

조명용 LED의 스위칭 구동 회로로 변조되는 가시광 통신 시스템의 구현

본 논문에서는 조명용 LED(Light Emitting Diode)의 스위칭 구동 회로를 이용한 변조 기법으로 조명 기능과 무선 통신 기능을 동시에 수행하는 가시광 통신(VLC: Visible Light Communication) 시스템을 제안하였다. 본 방식은 기존의 선형 영역에서 동작하는 LED 구동 회로를 갖는 가시광 통신 시스템에 비해 고효율이므로 고출력의 조명용 LED 시스템에 적용할 수 있는 장점이 있다. 제안된 시스템의 유용성을 입증하기 위하여 디지틀 방식의 오디오 시스템을 채용하여 가시광 통신 시스템을 구현하고, 그 실험 결과를 제시함으로써 제안된 방식의 우수성을 검증하였다. 실험 결과, 제안 회로의 시작품은 특별한 광필터 없이 20 W급 조명을 사용해서 약 1.5 m의 반경에서 최대 10 Mbps의 데이터 전송률을 달성하였다. In this paper, visible light communication(VLC) system modulated by a switching driver circuit of lighting light emitting diode(LED), not only for illumination but also for optical wireless communication, is implemented. Presented system could overcome the drawbacks of prior linear modulation technique such as low efficiency, heat generation, and limits to realization of high power lighting LED. Experimental results from the realized digital audio system are presented to confirm the superiority of the proposed circuit. Our prototype achieves a transmission data rate of 10 Mbps with a radius of 1.5 meters using 20 W output power, and the signals were detected successfully.

와이브로 기지국 시스템을 위한 고전력 PIN 다이오드 스위치 모듈과 고속 스위치 구동회로의 구현

본 논문에서는 와이브로 기지국 시스템을 위한 고전력 PIN 다이오드 스위치와 고속 스위치 구동회로에 대한 설계와 측정 결과를 제공한다. 일반적인 전력용 팩키지 다이오드의 기생 인덕턴스에 의한 격리도 열화를 막고 다이오드 스위치의 전력 능력을 향상시키기 위해 칩 형태의 다이오드를 사용하였으며, 본딩 와이어에 의한 직렬 인덕턴스는 전송선로의 임피던스에 쉽게 흡수될 수 있도록 회로를 구성하였다. 구현된 스위치 모듈은 사용된 다이오드의 개수를 최대한 줄이면서 최대의 성능을 얻을 수 있도록 설계되었으며 2.35 GHz에서 써큘레이터의 손실을 포함하여 약 0.84 dB의 삽입 손실과 80 dB 이상의 격리도 특성을 보였다. 또한 TTL 신호를 통한 스위치 모듈의 제어를 위해 스위치 구동회로를 설계, 제작하였으며 스위칭 속도는 200 nsec로 측정되었다. 스위치 모듈은 디지털 변조된 고전력 신호에 의해 전력능력이 시험되었으며 70 W의 전력이 인가되는 경우에도 정상적으로 동작하는 특성을 보여주었다. In this paper, the design and implementation of high-power PIN diode switch modules and high-speed switch driver circuits are presented for Wibro base stations. To prevent isolation degradation due to parasitic inductances of conventional packaged PIN diodes and to improve power handling capabilities of the switch modules, bare diode chips are used and carefully placed in a PCB layout, which makes bonding wire inductances to be absorbed in the impedance of a transmission line. The switch module is designed and implemented to have a maximum performance while using a minimum number of the diodes. It shows an insertion loss of <TEX>${\sim}0.84\;dB$</TEX> and isolation of 80 dB or more at 2.35 GHz. The switch driver circuit is also fabricated and measured to have a switching speed of <TEX>${\sim}200\;nsec$</TEX>. The power handling capability test demonstrates that the module operates normally even under a digitally modulated 70 W RF signal stress.

A monolithic HEMT passive switch with integrated HBT standard logic compatible driver for phased-array applications

We have achieved the first demonstration of a monolithically integrated high electron mobility transistor (HEMT) passive switch with a heterojunction bipolar transistor (HBT) switch-driver circuit that represents key integrated mixed-signal functions. The HEMT-HBT monolithic microwave integrated circuit (MMIC) is fabricated using selective molecular beam epitaxy (MBE). The single HEMT series switch is driven by an HBT circuit that provides both level shifting and wide voltage drive swing to adequately turn the passive HEMT switch device on and off. The MMIC can be made compatible for operation from either standard TTL or CMOS control signals. The series 0.2×200 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> passive HEMT switch achieves 1.6-2.9 dB insertion loss over a 50 MHz to 12 GHz band when the HEMT is turned on. The corresponding return-losses are >10 dB across the band. When the switch is turned off, the isolation ranges from >40 dB at 1 GHz and decreases to 15 dB at 12 GHz. This integrated HEMT switch and HBT switch driver MMIC represents a basic building block that can be applied to programmable phase shifters used in phased-array antenna applications and can result in a dramatic reduction in size and improvement in performance of these systems.

Design optimization and testing of a GaAs switched-capacitor filter

The design of GaAs MESFET technology is discussed. The design techniques developed are illustrated by means of a second-order switched-capacitor bandpass filter designed to operate at a switching frequency of 500 MHz. The design incorporates an operational amplifier architecture with a simulated gain of 60 dB and a switch driver circuit. Amplifiers are characterized in terms of settling time performance, and a general procedure for optimization of the switched-capacitor circuit to maximize switching frequency is presented. Measurements on a fabricated chip confirm the design of the filter and its components.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Switch-driver circuit suitable for high-order switched-capacitor filters implemented in GaAs

The author describes a new switch-driver circuit for use in GaAs switched-capacitor filter circuits having reasonable dynamic range. The circuit is compared by computer simulation with previous proposed circuits; it is shown that a significant reduction in the power dissipation and the dependence of clock feedthrough on the analogue signal level may be achieved. The circuit will allow the realisation of GaAs switched-capacitor filters having greater accuracy and order than has hitherto been feasible. >