Switch Block Research Articles

Predictive alternating runs and random task-switching sequences produce dissociative switch costs in the Consonant-Vowel/Odd-Even task.

Task-switching is commonly used to investigate working memory and attentional control processes. The current study compares predictive versus non-predictive task-sequencing effects on task-switching performance. Participants completed four blocks of the Consonant-Vowel/Odd-Even (CVOE) task: Two single task pure blocks, a predictable switch block where task switching occurred every two trials, and a random switch block where switching was unpredictable. In addition to mean error rates and response times (RTs), we assessed sequence effects on local switch costs (i.e., switch vs. nonswitch trials) and global costs (i.e., nonswitch vs. pure trials) for both error rates and RTs along with their underlying distributions. Overall, we show that while predictive and random switching produced similar patterns for mean error rates and RTs, a dissociation occurred in RT switch costs. When switching was random, local costs were inflated. In contrast, predictive switching increased global costs. Increased local costs for random versus predictive switching reflect an increase in task-setreconfiguration processes as participants struggle to reconfigure to an unpredictable task type in working memory on a subsequent trial. Separately, increased global costs for predictive switching reflect declines in task-set maintenance processes, as participants must maintain both task types in working memory while simultaneously monitoring their progress through the trial sequencing.

Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm

A new area model for estimating the layout area of switch blocks is introduced in this work. The model is based on a realistic layout strategy. As a result, it not only takes into consideration the active area that is needed to construct a switch block but also the number of metal layers available and the actual dimensions of these metals. The model assigns metal layers to the routing tracks in a way that reduces the number of vias that are needed to connect different routing tracks together while maintaining the tile-based structure of FPGAs. It also takes into account the wiring area required for buffer insertion for long wire segments. The model is evaluated based on the layouts constructed in the ASAP7 FinFET 7nm Predictive Design Kit. We found that the new model, while specific to the layout strategy that it employs, improves upon the traditional active-based area estimation models by considering the growth of the metal area independently from the growth of the active area. As a result, the new model is able to more accurately estimate the layout area by predicting when the metal area will overtake the active area as the number of routing tracks is increased. This ability allows the more accurate estimation of the true layout cost of FPGA fabrics at the early floor planning and architectural exploration stage; and this increase in accuracy can encourage a wider use of custom FPGA fabrics that target specific sets of benchmarks in future SOC designs. Furthermore, our data indicate that the conclusions drawn from several significant prior architectural studies remain to be correct under FinFET geometries and wiring area considerations despite their exclusive use of active-only area models. This correctness is due to the small channel widths, around 30–60 tracks per channel, of the architectures that these studies investigate. For architectures that approach the channel width of modern commercial FPGAs with more than 100–200 tracks per channel, our data show that wiring area models justified by detailed layout considerations are an essential addition to active area models in the correct prediction of the implementation area of FPGAs.

Multiple decrements in switch task performance in female rats exposed to space radiation

Astronauts on the Artemis missions to the Moon and Mars will be exposed to unavoidable Galactic Cosmic Radiation (GCR). Studies using male rats suggest that GCR exposure impairs several processes required for cognitive flexibility performance, including attention and task switching. Currently no comparable studies have been conducted with female rats. Given that both males and females will travel into deep space, this study determined whether simulated GCR (GCRsim) exposure impairs task switching performance in female rats. Female Wistar rats exposed to 10 cGy GCRsim (n = 12) and shams (n = 14) were trained to perform a touchscreen-based switch task that mimics a switch task used to evaluate pilots’ response times. In comparison to sham rats, three-fold more GCRsim-exposed rats failed to complete the stimulus response stage of training, a high cognitive loading task. In the switch task, 50% of the GCRsim-exposed rats failed to consistently transition between the repeated and switch blocks of stimuli, which they completed during lower cognitive loading training stages. The GCRsim-exposed rats that completed the switch task only performed at 65% of the accuracy of shams. Female rats exposed to GCRsim thus exhibit multiple decrements in the switch task under high, but not low, cognitive loading conditions. While the operational significance of this performance decrement is unknown, if GCRSim exposure was to induce similar effects in astronauts, our data suggests there may be a reduced ability to execute task switching under high cognitive loading situations.

CCS-Net: Cascade Detection Network With the Convolution Kernel Switch Block and Statistics Optimal Anchors Block in Hypopharyngeal Cancer MRI.

Magnetic resonance imaging (MRI) is a common diagnostic method for hypopharyngeal cancer (HPC). It is a challenge to automatically detect HPC tumors and swollen lymph nodes (HPC risk areas) from MRI slices because of the small size and irregular shape of HPC risk areas. Herein, we propose a cascade detection network with Convolution Kernel Switch (CKS) Block and Statistics Optimal Anchors (SOA) Block in HPC MRI (CCS-Net). CKS Block can adaptively switch standard convolution to deformable convolution in some appropriate layers to detect irregular objects more efficiently without taking up too much computing resources. SOA Block can automatically generate the optimal anchors based on the size distribution of objects. Compared with other methods, our method achieves splendid detection performance and outperforms other methods on the HPC dataset (more than 1800 T2 MRI slices), achieving the highest AP50 of 78.90%. Experiments show that the proposed network can be the basis of a computer aided diagnosis utility that helps achieve faster and more accurate diagnostic decisions for HPC.

Dynamic Reconfiguration of PV Array under Partial Shading Condition by Using Automatic Switching

The mismatching effect caused by partial shade is one of the critical problems in the operation of photovoltaic (PV) arrays, it can cause large losses in the power produced by the PV system. Power losses due to partial shading (PS) for a particular operating situation may be controlled by altering the PV array's scheme connection. For that reason, this paper presents an Automatic Switch Block (ASB) based on dynamic relays without using an algorithm to control the connection between PV panels to reduce the effect of partial shading and provide the ability of scaling. The Simulation results showed that the proposed module has a high ability and efficiency in mitigating and reducing the effect of partial shade on solar panel arrays by automatically changing the electrical connection between the panels compared with total cross-tied (TCT), Futoshiki puzzle pattern (FPP), Sudoku and L-Shape Algorithm. Moreover, the proposed method was tested in SIMULINK/MATLAB environment for different shading patterns and achieved an improvement in maximum power point tracking (MPPT) by about 12% as compared with L-Shape, more than 30% compared to TCT, and about 15% for other methods.

An Optimized GIB Routing Architecture with Bent Wires for FPGA

Field-programmable gate arrays (FGPAs) are widely used because of the superiority in flexibility and lower non-recurring engineering cost. How to optimize the routing architecture is a key problem for FPGA architects because it has a large impact on FPGA area, delay, and routability. In academia, the routing architecture is mainly based on the connection blocks (CBs) and switch blocks (SBs), whereas most research has focused on SB architectures, such as Wilton, Universal, and Disjoint SB patterns. In this article, we propose a novel unidirectional routing architecture—general interconnection block (GIB)—to improve FPGA performance. With the GIB architecture, logic block (LB) pins can directly connect with the adjacent GIBs without programmable switches. Inside a GIB, LB pins can connect to the routing channel tracks on the four sides of a GIB. In particular, the logic pins from different neighboring LBs that connect to the same GIB can connect with each other with only one programmable switch. In addition, we enhance VTR to support the GIB with bent wires and develop a searching framework based on the simulated annealing algorithm to search for a near-optimal distribution of wire types. We evaluate the GIB architecture on VTR 8 with the provided benchmark circuits. The experimental results show that the GIB architecture with length-4 wires can achieve 9.5% improvement on the critical path delay and 11.1% improvement on the area-delay product compared to the VTR CB-SB architecture with length-4 wires. After exploring mixed wire types, the optimized GIB architecture can further improve the delay by 16.4% and area-delay product by 17.1% compared to the CB-SB architecture with length-4 wires.

Systematic realization of non-linear arithmetic functions using hexagonal Field Programmable Analog Array

In spite of being the most popular reconfigurable platform for analog and mixed-mode design implementation, Field-Programmable Analog Array (FPAA) structures are limited to analog filters, amplifiers and communication circuits. Hexagonal FPAA is an established alternative to classical square-lattice FPAA but suitable architectures have not been cultivated much. In this paper, a hexagonal FPAA, implementing different nonlinear functions, eliminating global interconnections, and employing a graph-based mapping algorithm, has been proposed. For communication among the fundamental blocks and reconfiguration, it uses a local interconnection network consisting of central and corner switch blocks. The proposed mapping algorithm uses directed graph representations of fundamental blocks and desired circuits to map the nonlinear functions in the presented FPAA. Weights have been assigned to the graphs and manipulated for efficient placement and routing. All the theoretical predictions have been validated through SPICE simulation using 65 nm CMOS technology. The proposed architecture and mapping algorithm can be extended for large-scale FPAA enriched with automatic placement and routing tools.

Measuring the effect of track count and wire segment length on the layout area of switch blocks for tile-based FPGAs

Switch block flexibility is an important design metric in FPGA architectural research. A switch block with high flexibility can provide better routability for implementing digital applications, which can lead to better performance and logic density. Flexibility, however, does come at the cost of an increase in the layout area of switch blocks, which can lower performance and logic density. Consequently, it is important to accurately estimate the layout area of increasing switch block flexibility in order to better design FPGA architectures. This work focuses on the popular disjoint switch block design and evaluates the accuracy of the traditional active-based area estimation models based on realistic layouts. We found that the current active-based area models are inaccurate in estimating the true area cost of increasing switch block flexibility. This inaccuracy is due to the inability of the current models to consider the full effect of routing track count and wire segment length, two important flexibility parameters, on the layout area of switch blocks. We found that by including wiring area into the estimation of FPGA switch block layout area, one can significantly improve the accuracy of predicting the true area cost of these flexibility parameters. These results allow FPGA architects to better optimize future FPGA designs for routability and consequently for performance and logic density.

Optimum network configuration design of a multi-beam vortex-induced vibration piezoelectric energy harvester

The focus of this study is on multi-beam piezoelectric energy harvester (MPEH) network optimization with respect to its configuration. Indeed, the harvested power in the single piezoelectric energy harvesters (SPEHs) may not meet the power level necessary to many applications. In case of constraint in the beam dimensions, the issue of sufficient power generation can be undertaken by arranging a definite number of those harvester units as an MPEH network. The versatility of network configurations presented in the literature, consisting of the harvester beams and their series/parallel interconnections, are limited to only two scenarios including all-series and all-parallel connections of the beams. As will be shown, these classic configurations are not necessarily the optimum ones for a given vortex shedding (VS) frequency. In fact, the harvested power as a function of VS frequency can be maximized by adopting a special network configuration, referred to as the optimum network configuration (ONC). In this study, the general form of the harvested power for each VS frequency is presented in a closed-form expression as a function of the network parameters. An optimization problem is formulated to maximize the harvested power and to obtain the ONC, which is solved through a proposed algorithm named the network configuration optimizer (NETCOOP). In the proposed MPEH structure, electrical switch blocks are used to implement the ONC and to reconfigure the network according to each VS frequency. The obtained VS frequency-dependent ONC enables the designers to develop the best configuration at each fluid flow velocity. To highlight the advantages of this proposed algorithm, the performance of the ONC is compared with other configurations like the all-series and the all-parallel configurations. In the simulation results, the optimum harvested power is obtained for different VS frequencies and load resistances by applying the brute-force approach. It is revealed that the harvested power obtained by the NTECOOP algorithm matches the optimum performance.

A New Hybrid Voltage Source Converter With Reduced Active Switch Count for HVDC Applications

This paper presents a new hybrid voltage source converter topology with reduced active switch count for HVDC applications. It consists of a block of switches in the upper converter arms and cascaded switch-diode cells in the lower converter arms. The cascaded switch-diode cells in the lower converter arms produce a multilevel output voltage while the switch blocks in the upper converter arms perform rectification. The switches in the upper converter arms conduct for one-third of the fundamental line period as dictated by the relative magnitude of the input line-to-neutral voltages. Only one of the three phase blocks of switches conduct at a time. Compared to other voltage source converter topologies with similar structure and operation to this topology, the proposed topology has lower number of devices. Therefore, it has lower converter footprint and cost. More importantly, it reduces the semiconductor device power losses significantly due to the lower number of active switches (lower switching loss) and the lower number of devices in current conduction path (lower conduction loss). The basic operation principle of the proposed converter and its associated control strategy that regulates the power exchange between the converter, and the ac and dc networks are described in detail and verified using both simulation and experimental results.

Highly Selective Bandpass Switch Block With Applications of MMIC SPDT Switch and Switched Filter Bank

A new bandpass single-pole single-throw (SPST) switch (BPSW) is proposed in this letter. The proposed BPSW configuration can be directly employed as a building block to construct the single-pole N-throw (SPNT) switch or the highly-selective switched filter bank with no need for the extra control circuit, thus effectively reducing the circuit size and lowering the loss. The operation mechanism of the BPSW is analyzed, and the filter-synthesis-based design method is given. For demonstration, 3-6 GHz and 4-8 GHz BPSW blocks are built using the commercial GaAs pHEMT process to construct the single-pole double-throw (SPDT) switch as well as the two-way integrated switched filter bank. The filter bank is implemented in 0.25 μm GaAs pHEMT process. Two passbands are measured at 2.7-5.79 GHz and 3.72-7.35 GHz with a minimum insertion loss of 2.7 dB, while the all-OFF state can be set with over 35 dB suppression. The measurement results are in good agreement with the simulation that verifies the concept.

Conduction mechanism effect on physical unclonable function using Al2O3/TiOX memristors

In this study, we evaluate the performance of a physical unclonable function (PUF) using Al2O3/TiOx based memristors. Through a conduction mechanism analysis, it is confirmed that the distribution of high-resistance state (HRS) is wider than that of low-resistance state (LRS) due to the direct-tunneling gap. Furthermore, cycle-to-cycle variation and random telegraph noise (RTN) characteristics which can affect the reliability of the PUF are also analyzed. Since the switching characteristics of the devices are less affected by temperature in the LRS thanks to ohmic conduction, the device state of a whole array is determined as the LRS for a better reliability. In addition, three kinds of response extraction methods are compared by evaluating the diffuseness and uniqueness with 2 × 2 switch block for the improved randomness. Finally, the reliability of the PUF is verified considering the measured conductance dependency on temperature and noise effect, and the bit error rates are compared between two states.

Design of Automatic Rain Gauge Prototype (ARG) As An Early Warning Indicator for Cold Lava Flood Based on The Internet of Things (IoT)

This study aims to design a prototype of automatic rain gauge, characterize the automatic rain gauge, rainfall classification as an indicator of cold lava flood, tested the automatic rain gauge prototype. The design of this tool includes three parts, the first is the reed switch block design. Second, designing an automatic rain gauge block by designing a tipping bucket. The third is designing IoT block and Android applications. The automatic rain gauge prototype was successfully designed with a 0.8 cm reed switch and a tipping bucket with a funnel area of 380 cm2 with a resolution of 0.1 mm and a maximum capacity of 9.4 mm/minute. The classification of rainfall as an indicator of cold lava flood is normal 0-15 mm, advisory 16-20 mm, watch 21-48 mm and warning > 48 mm, so that the early warning system prototype can display rainfall charts and warning alarms on the android application.

FIFA: A Fully Invertible FPGA Architecture to Reduce BTI-Induced Aging Effects

FPGAs are increasingly becoming sensitive to aging effects mainly through BTI phenomena in the latest technology nodes. This phenomenon can be modeled as a shift in the threshold voltage of transistors which leads to performance degradation and reduction in SNM of SRAM cells. To reduce the aging effects on FPGA building blocks, we propose FIFA, a fully invertible FPGA architecture. In this architecture, two small modules are introduced to make the bitstream of logic and routing resources of the FPGA tiles fully invertible. Accordingly, to insert recovery cycles in the lifetime of the transistors, the bitstream stored in the configuration SRAM cells can be inverted occasionally without any changes in the functionality of the design. Using the proposed architecture, it is neither required to repeat the placement and routing procedures to generate multiple configuration bitstreams, nor extra memory is needed to save alternative bitstreams for changing the SRAM cells contents. Our experimental results over a set of industrial benchmarks show that by choosing an appropriate switch block arrangement and an optimized flipping frequency, the proposed architecture can improve the aging induced performance degradation by up to 62.5% with acceptable power and area overheads on logic and routing resources.

Scaling Trends of Monolithic 3-D Complementary Metal–Oxide–Semiconductor Nanoelectromechanical Reconfigurable Logic Circuits

The scaling trends of monolithic 3-D (M3-D) complementary metal-oxide-semiconductor (CMOS) nanoelectromechanical (NEM) reconfigurable logic (RL) circuits are compared with CMOS-only circuits for the first time. It is confirmed that M3-D CMOS-NEM RL circuits are superior to CMOS-only circuits in terms of propagation delay, power consumption, and power-delay product (PDP) because of the low resistance and full signal swing of NEM memory switches that not only affect the current switch block but also the following block. Because the performance, power, and energy gains of the CMOS-NEM RL circuits over CMOS-only circuits increase as the technology node improves, M3-D CMOS-NEM RL circuits can be considered as one of the most promising candidates for high-density, high-performance, and low-power RL circuits.

Design and simulation of high-performance 2:1 multiplexer based on side-contacted FED

Designing a high-quality switch block ensures the efficient data transmission in digital circuits and systems. In this paper, an innovative 2:1 multiplexer is successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs) at 180 nm SOI technology node. Optimization of the reservoir thickness and gate work function of the S-FED satisfy high ION/IOFF ratio and noise-immunity. DC, AC, and transient mixed-mode simulations are employed to scrutinize and compare performance of constituent logic gates based on the S-FED and CMOS. Simulation results demonstrate superior noise margins up to 100 mV for the S-FED-based inverter compared with the CMOS-based counterpart. Furthermore, the S-FED-based transmission gate with switching frequency of 38.9 GHz can act as a high-speed alternative for the CMOS-based one. Both multiplexer architectures configured by the S-FED and CMOS are compared in terms of performance parameters. In this regard, average power consumption and PDP quantities for the S-FED-based multiplexer reveal significant reductions by about 2 and 3 orders of magnitude, respectively, compared with the CMOS-based one. In addition, propagation delay time increases drastically with scaling power supply in the CMOS-based multiplexer; while, this increase is suppressed for the S-FED-based version.

Push-pull microring-assisted space-and-wavelength selective switch.

We introduce a novel design of a space-and-wavelength selective switch based on microring-assisted Mach-Zehnder interferometers. Multiple pairs of overcoupled microring resonators are incorporated as efficient and narrowband phase shifters and are driven in push-pull scheme. We design and demonstrate a 2×2×2λ elementary switch block with full spatial and spectral switching capabilities. The switching device's cross talk suppression and extinction ratio both exceed 21 dB. We measure over 75 GHz optical bandwidth per channel and less than 1.5 dB power penalty at 10-9 BER when two 32 Gbps on-off keying signals are loaded simultaneously. This new class of switching elements can further enable compact and high-performance space-and-wavelength selective switch fabrics without the need for wavelength (de)multiplexers or parallel switching planes.

Within-person increase in pathological worry predicts future depletion of unique executive functioning domains.

Affective neuroscience and scar theories propose that increased excessive worry, the hallmark symptom of generalized anxiety disorder (GAD), predicts future declines in executive functioning (EF). However, the preponderance of cross-sectional designs used to examine between-person chronic worry-EF relationships has blocked progress on understanding their potentially causal within-person associations. Accordingly, this study used bivariate dual latent change score (LCS) models to test whether within-person increased GAD severity might relate to future reduced EF. Community-dwelling adults (N = 2581, 46 years on average, s.d. = 11.40, 54.71% female) were assessed for GAD symptom severity (Composite International Diagnostic Interview-Short Form) across three waves, spaced about 9 years apart. Three aspects of EF [inhibition, set-shifting, and mixing costs (MCs; a measure related to common EF)], were assessed with stop-and-go switch tasks. Participants responded to 20 normal and 20 reverse single-task block trials and 32 mixed-task switch block trials. EF tests were administered at time 2 (T2) and time 3 (T3), but not at time 1 (T1). After controlling for T1 depression, LCS models revealed that within-person increased T1 - T2 GAD severity substantially predicted future reduced T2 - T3 inhibition and set-shifting (both indexed by accuracy and latency), and MC (indexed by latency) with moderate-to-large effect sizes (|d| = 0.51-0.96). Results largely support scar theories by offering preliminary within-person, naturalistic evidence that heightened excessive worry can negatively predict future distinct aspects of cognitive flexibility. Effectively targeting pathological worry might prevent difficulties arising from executive dysfunction.

Vortex Express Method for Parameter Determination Thermoelectric Materials

The method is based on the possibility of determining the heat loss of electric power during the flow of Foucault eddy currents in the volume of a thermoelectric sample, placing in the field of action of the ferrite core an inductor through which electric currents that are symmetrical and asymmetric in nature flow sequentially in time.
 Mathematical expressions are obtained for the coefficients of electrical conductivity σ, thermal conductivity ϰ, thermo-emf α and thermoelectric figure of merit Z. Minimization of the error of the proposed method, carried out by computer simulation of the physical processes occurring in the sample using appropriate programs, showed that the operating frequency of the device measuring sensors should be located in the range of 36 ÷ 250 kHz, and the electric current flowing through it — taking into account the inequality qф/П/ qф/ qϰ > 10. The magnetic field induction ratio in terms of components is selected from the condition В0/В > 8.6, which corresponds to the conditions of minimal impact on the parameters of the sample by galvanic thermomagnetic phenomena.
 The block diagram of a device for non-contact measurement of symmetric σс and asymmetric σа components of the electrical conductivity of thermoelectric materials consists of: 1 — SV switch block; 2 — electronic switch; 3 — auto generator; 4 — AC amplifier; 5 — synchronous detector; 6 — DC amplifier; 7 — pulse generator; 8 — signal processing unit; 9 — indicator device; 10 — DC indicator; 11 — correction unit; FR1, FR2.
 Measurement of the parameters of the thermoelectric sample based on Bi-Te-Se-Sb crystals showed that the real error of the proposed method is 2 %. This indicates that the eddy current method can be successfully used to determine the main parameters of thermoelectric materials.
 The use of this method allows solving the relevant problem of avtomazation of the process of monitoring and sorting out thermoelectric ingots, billets and parts.

Low-Power Crossbar Switch With Two-Varistor Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA

A nonvolatile and programmable routing switch featuring two-varistor selected complementary atom switch (2V-1CAS also known as via-switch) is evaluated. The a-Si/SiN/a-Si varistor as a selector for the atom switch shows superior nonlinear current–voltage characteristics with high selectivity of ~105, which originates from the staircase barrier height in the layers. The two control lines connected to the varistors realize multiple fan-outs of the crossbar switch without select transistors. The $50\,\,\sf \times20$ crossbar switch block is demonstrated, where the atom switch is placed at each cross point and programmed through the varistors. The developed via-switch crossbar switch is a strong candidate for achieving energy-efficient nonvolatile field-programmable gate array in the Internet-of-Things applications.