Switch Architecture Research Articles

Two‐mode multiplexed Fourier‐based labels

AbstractA two‐mode optical packet switching architecture using an optical multiport mode‐division multiplexing label generator and processor is proposed. By combining optical labels on two modes, the number of labels is increased exponentially. Beat noise significantly affects the label error rate, when multimode crosstalk is maximum. This impairment can be mitigated by time shifting the optical labels of the two modes by half of the label duration.

An efficient and improved algorithm for generating an equivalent planar architecture of the data vortex switch

The data vortex (DV) switch was originally designed as an all optical interconnection network for high performance computing (HPC) applications. It was highly scalable with low latency and high throughput, compared to traditional switches used for optical packet switching (OPS) and HPC applications. The equivalent planar (chained MIN) model of the DV, proposed in previous literature, is a planar diagrammatic conversion of a 3-D model of the DV network. In this paper, we will focus on exploring a new, efficient and improved generalized algorithm that enables the arrangement of routing pathways to be implemented as an equivalent planar architecture (EPA, chained MIN) of a DV to find all possible routes between each source and target node pair. The original 3-D architecture of any size can be converted to a planar structure more simply by using the new generalized equivalent planar architecture (EPA) algorithm. To verify the proposed EPA algorithm, it was tested with different input traffic loads and network sizes while keeping the active angle ‘A’ constant. Network performance parameters, including injection rate (throughput) and latency (mean hops), obtained from simulation results are also provided to confirm the validity of the proposed EPA algorithm. This new algorithm is versatile, simple and can be applied to networks of various sizes.

Scaling wavelength selective switches for multi-band and space-division-multiplexed networks

This paper investigates the practical scalability of wavelength selective switching technology for the emerging multi-band and space-division-multiplexed (SDM) networks. Wavelength selective switching architectures are introduced for multi-band SDM networks. The switching capacity is analyzed for both weakly coupled and strongly coupled SDM networks. Key bottlenecks for scaling up toward multi-band and more spatial modes are identified. Contrary to the conventional view that liquid crystal on silicon (LCOS) was the only technological obstacle, the manufacturability of free-space optics with high numerical apertures and constraints on the optical dimensions also brought significant challenges for the development of highly integrated wavelength selective switches for multi-band SDM networks.

Binding-induced activation of CRISPR-Cas12a using PAM-engineered toehold switch and DNA tile architectures for enhanced detection of thrombin

This study presents a novel biosensor that integrates CRISPR-Cas12a technology with DNA tile-based architectures to enhance thrombin detection. Utilizing PAM-engineered toehold switches, the biosensor dynamically activates the CRISPR-Cas12a system upon thrombin recognition, significantly improving both sensitivity and specificity. The label-free electrochemical detection method offers rapid, cost-effective analysis, making it ideal for real-time clinical applications. The biosensor achieved an impressive detection limit of 103 aM, surpassing traditional methods and setting a new standard for thrombin assays. The biosensor's robust performance in complex biological samples, such as diluted human serum, demonstrates its reliability for clinical diagnostics. This is particularly important for the early diagnosis and management of thrombotic and coagulation-related disorders. By combining advanced genetic engineering with traditional electrochemical techniques, the biosensor not only optimizes detection but also expands its potential applications across various biomedical fields. Overall, this biosensor provides a powerful and innovative tool for thrombin detection, offering enhanced diagnostic accuracy, faster patient management, and potential cost savings in healthcare. Its superior performance and adaptability highlight its promise for broader adoption in clinical diagnostics and other biosensing applications.

Effects of packetization on communication dynamics in brain networks.

Computational studies in network neuroscience build models of communication dynamics in the connectome that help us understand the structure-function relationships of the brain. In these models, the dynamics of cortical signal transmission in brain networks are approximated with simple propagation strategies such as random walks and shortest path routing. Furthermore, the signal transmission dynamics in brain networks can be associated with the switching architectures of engineered communication systems (e.g., message switching and packet switching). However, it has been unclear how propagation strategies and switching architectures are related in models of brain network communication. Here, we investigate the effects of the difference between packet switching and message switching (i.e., whether signals are packetized or not) on the transmission completion time of propagation strategies when simulating signal propagation in mammalian brain networks. The results show that packetization in the connectome with hubs increases the time of the random walk strategy and does not change that of the shortest path strategy, but decreases that of more plausible strategies for brain networks that balance between communication speed and information requirements. This finding suggests an advantage of packet-switched communication in the connectome and provides new insights into modeling the communication dynamics in brain networks.

Implementation and testing of a KNS topology in an InfiniBand cluster

The InfiniBand (IB) interconnection technology is widely used in the networks of modern supercomputers and data centers. Among other advantages, the IB-based network devices allow for building multiple network topologies, and the IB control software (subnet manager) supports several routing engines suitable for the most common topologies. However, the implementation of some novel topologies in IB-based networks may be difficult if suitable routing algorithms are not supported, or if the IB switch or NIC architectures are not directly applicable for that topology. This work describes the implementation of the network topology known as KNS in a real HPC cluster using an IB network. As far as we know, this is the first implementation of this topology in an IB-based system. In more detail, we have implemented the KNS routing algorithm in the OpenSM software distribution of the subnet manager, and we have adapted the available IB-based switches to the particular structure of this topology. We have evaluated the correctness of our implementation through experiments in the real cluster, using well-known benchmarks. The obtained results, which match the expected performance for the KNS topology, show that this topology can be implemented in IB-based clusters as an alternative to other interconnection patterns.

Bayesian learning of nonlinear gene regulatory networks with switching architectures

Introduction: Gene regulatory networks (GRNs) are characterized by their dynamism, meaning that the regulatory interactions which constitute these networks evolve with time. Identifying when changes in the GRN architecture occur can inform our understanding of fundamental biological processes, such as disease manifestation, development, and evolution. However, it is usually not possible to know a priori when a change in the network architecture will occur. Furthermore, an architectural shift may alter the underlying noise characteristics, such as the process noise covariance.Methods: We develop a fully Bayesian hierarchical model to address the following: a) sudden changes in the network architecture; b) unknown process noise covariance which may change along with the network structure; and c) unknown measurement noise covariance. We exploit the use of conjugate priors to develop an analytically tractable inference scheme using Bayesian sequential Monte Carlo (SMC) with a local Gibbs sampler.Results: Our Bayesian learning algorithm effectively estimates time-varying gene expression levels and architectural model indicators under varying noise conditions. It accurately captures sudden changes in network architecture and accounts for time-evolving process and measurement noise characteristics. Our algorithm performs well even under high noise conditions. By incorporating conjugate priors, we achieve analytical tractability, enabling robust inference despite the inherent complexities of the system. Furthermore, our method outperforms the standard particle filter in all test scenarios.Discussion: The results underscore our method’s efficacy in capturing architectural changes in GRNs. Its ability to adapt to a range of time-evolving noise conditions emphasizes its practical relevance for real-world biological data, where noise presents a significant challenge. Overall, our method provides a powerful tool for studying the dynamics of GRNs and has the potential to advance our understanding of fundamental biological processes.

Optical switching will innovate intra data center networks [Invited Tutorial

Reflecting the recent slow-down in Moore’s law and the proliferation of artificial intelligence/machine learning workloads, the performance and energy consumption of networks are becoming barriers in high-performance computing (HPC) and data centers. Optical switches are expected to break these barriers, and indeed their introduction has recently commenced in data centers. This paper discusses how optical switching technologies can innovate future intra data center networks. Hyperscale data centers are much bigger in scale, and network requirements are slightly different from those of HPC. This paper focus on data center networks, since the impact of optical technologies will be more significant in data centers than in HPC. In addition to the scale issue, important metrics to be considered for network design are traffic characteristics and latency, both of which are highlighted in this paper. For hybrid (electrical packet and optical circuit) switching networks, the target latency for the optical circuit switch network (connection setup/teardown time) is shown to be around 10 µs, and the needed technologies are clarified and verified by experiments. The optical switch can simplify the present multi-tier switching network above tier-1 switches into a single tier configuration, which is possible with the development of efficient large port count optical switches. Among the different switching architectures, combining the different dimensions of space and wavelength is shown to be one of the best solutions. Fast switching needs fast device response time. Si photonics devices using Mach–Zehnder interferometers or ring-resonator-based switches and tunable filters are the most promising candidates; they offer cost-effective mass-production and fast operation and so are excellent candidates for the optical switches envisaged. Another critical technology to maximize the benefits of optical switches is a simple and low-latency control mechanism. Different approaches have been suggested as summarized in this work. Among them, harnessing optical switch parallelism is a unique technique that matches recent advances in electrical switch chips. A fast control network is realized by using a fully decentralized and asynchronous control mechanism. A hyperscale data center offers a wide variety of services, and no one system fits all needs. Optimization of parameters is an important task for maximizing the impact of optical switching in different kinds of data centers.

First operation of the JUNGFRAU detector in 16-memory cell mode at European XFEL

The JUNGFRAU detector is a well-established hybrid pixel detector developed at the Paul Scherrer Institut (PSI) designed for free-electron laser (FEL) applications. JUNGFRAU features a charge-integrating dynamic gain switching architecture, with three different gain stages and 75 μm pixel pitch. It is widely used at the European X-ray Free-Electron Laser (EuXFEL), a facility which produces high brilliance X-ray pulses at MHz repetition rate in the form of bursts repeating at 10 Hz. In nominal configuration, the detector utilizes only a single memory cell and supports data acquisition up to 2 kHz. This constrains the operation of the detector to a 10 Hz frame rate when combined with the pulsed train structure of the EuXFEL. When configured in so-called burst mode, the JUNGFRAU detector can acquire a series of images into sixteen memory cells at a maximum rate of around 150 kHz. This acquisition scheme is better suited for the time structure of the X-rays as well as the pump laser pulses at the EuXFEL. To ensure confidence in the use of the burst mode at EuXFEL, a wide range of measurements have been performed to characterize the detector, especially to validate the detector alibration procedures. In particular, by analyzing the detector response to varying photon intensity (so called ‘intensity scan’), special attention was given to the characterization of the transitions between gain stages. The detector was operated in both dynamic gain switching and fixed gain modes. Results of these measurements indicate difficulties in the characterization of the detector dynamic gain switching response while operated in burst mode, while no major issues have been found with fixed gain operation. Based on this outcome, fixed gain operation mode with all the memory cells was used during two experiments at EuXFEL, namely in serial femtosecond protein crystallography and Kossel lines measurements. The positive outcome of these two experiments validates the good results previously obtained, and opens the possibility for a wider usage of the detector in burst operation mode, although compromises are needed on the dynamic range.

Integration and first operation of the Gotthard-II detector at European XFEL

Gotthard-II (G-II) is a 1-D silicon microstrip hybrid detector developed by the Paul Scherrer Institut within the framework of a collaboration agreement with the European XFEL. The ASIC features a dynamic gain switching architecture, in order to cope with the luminosity of European XFEL, and a 12-bit analog-to-digital converter with a sampling/conversion rate of more than 18 MS/s as well as a Static random-access memory, making it capable of matching the European XFEL pulse train structure, thus acquiring up to 2700 images at 4.5 MHz per burst. The sensor’s strip pitch can be either of 50 μm or 25 μm , for a total of 1280 or 2560 output channels per detector, respectively, with a spectral sensitivity that allows either X-ray detection (optimized in the 5–20 keV range) or visible light detection. Its exceptionally good compliance with the European XFEL beam conditions will make G-II the most widely employed detector across the facility, with a total of 29 modules of different flavors that will be installed in scientific instruments and beam diagnostic setups. Although the detector will be predominantly used for spectroscopic measurements it will have a variety of other applications, including X-ray diffraction/emission/absorption experiments, relative pulse arrival time monitoring (of fundamental importance for pump–probe experiments), spectral diagnostics, and beam quality monitoring, with the possibility for the detector itself to generate a veto patterns for the large area MHz framerate pixel detectors employed at the scientific instruments, such as AGIPD, LPD and DSSC. In this paper, an overview of G-II detector technology and its usage at the European XFEL will be presented; the focus will then move on towards the process of detector integration in the European XFEL control system, data acquisition, and data correction infrastructure, highlighting its challenges. Finally, an overview of the first results obtained at scientific instruments will be given.

High-temperature integrated SiC MOSFET bi-directional switch in power-overlay technology

Bi-directional power switch architectures are emerging as a key enabler of advanced integration and enhanced functionality options in modern motor-drive concepts targeting the development of more efficient, power dense and reliable solutions in energy-strategic applications ranging from transportation to air-conditioning, sewage and industrial. Specifically, wide-band-gap semiconductor based highly integrated solutions capable of withstanding high operational temperatures are required. Whereas with GaN, lateral devices, monolithic integration efforts are being pursued, the vertical structure of SiC transistors requires the development of bespoke packaging. This paper presents such a solution, based on the use of power overlay technology to yield a 200 °C validated power switch.

Comparative analysis of optical data center switches

Abstract In the recent past, there has been an explosive growth in data traffic within data center systems. This rapid increase in data volume has put significant constraints on the speed of current data communication networks, which are predominantly based on electronic controllers and memory. The speed limitations of electronic devices hinder their ability to process data at higher rates efficiently. To address this issue and enable faster data processing, the use of optical communication emerges as the most promising solution. Optical communication leverages the capabilities of light signals and optical components, which can handle data at much higher rates compared to their electronic counterparts. One key element in optical communication systems is the utilization of fiber delay lines (FDLs) as optical storage for packets. FDLs offer the ability to temporarily store and delay optical signals, providing buffering capabilities within optical networks. These FDLs can be configured in various setups, including feed forward, feed backward, and recirculating configurations, each with its own set of advantages and disadvantages. In this context, this article explores several state-of-the-art arrayed waveguide grating (AWG)-based optical packet switch (OPSW) architectures. These switches are designed to efficiently route and manage optical packets within data center networks. Each architecture is summarized, highlighting its unique features and capabilities. To compare the different AWG-based OPSW architectures, various key parameters are considered, such as the cost, physical losses, bit error rate (BER), and the number of tunable components required. These parameters are critical in determining the performance, efficiency, and cost-effectiveness of the switches.

Microwave Switch Architecture for Superconducting Integrated Circuits Using Magnetic Field-Tunable Josephson Junctions

We report on the design, fabrication, and measurement of a low-temperature microwave switch architecture that can be fully integrated on chip using single Josephson junctions and superconducting bias lines. The basic switching element used is a reflective single-pole-single-throw switch that is realized by tuning the critical current of a single Josephson junction by way of a local flux bias. A single-pole-single-throw switch is demonstrated at 4.2 K to have an on/off ratio in excess of 20 dB up to 12 GHz. This element is then incorporated into the design of a single-pole-double-throw switch that exhibits an on/off ratio above 20 dB up to 10 GHz. The switches require no intrinsic power dissipation in either state, and their performance was verified for input powers of -100 dBm to -60 dBm. S-parameter simulations using a simple lumped element model are in good agreement with the experimental data, allowing for the design to be extended to larger switch architectures.

New trends in photonic switching and optical networking architectures for data centers and computing systems [Invited

The rapid increases in data traffic coupled with user preferences are driving the data center and computing system service providers to offer energy-efficient, intelligent, flexible, cost-effective, high-capacity, and low-latency data services without added complexity to the users. Disaggregated heterogeneous reconfigurable computing systems realized by photonic switching and interconnects can enhance throughput and energy efficiency for artificial intelligence/machine learning (AI/ML) workloads, especially when aided by the AI/ML-enhanced control plane. Photonic switching and new optical networking architectures are expected to solve many of these challenging problems. This paper discusses new trends in photonic switching and optical network architectures for future data centers and computing systems summarized as follows: (1) flat reconfigurable disaggregated computing enabled by high-radix photonic switching and interconnects in data centers; (2) chiplet-based computing architectures empowered by embedded photonics toward heterogeneous reconfigurable computing; (3) nanosecond-scale photonic switching in data centers and computing systems; (4) AI/ML in self-driving, application-aware, and situation-aware data centers; (5) the emergence of flexible networking for cloud computing, edge computing, and split computing, as well as flexible networking for 5G/6G RF-optical networks; and (6) the deployment of embedded co-designed silicon photonics being considered for future data centers.

Low-loss microwave photonic switching for satellite communication.

For traditional switching architecture, packet switching performs fine granularity data packet forwarding, but its digital signal processing (DSP) has high power consumption (PC). All-optical switching provides rapid exchange of wavelength resources, which has coarse granularity. In scenarios where the PC is limited, such as broadband satcom, a switching architecture with lower PC and finer granularity than optical switching would be useful. In this paper, we propose a novel, to the best of our knowledge, low-loss microwave photonic switching architecture that can exchange subband signals across beams and frequency bands. The switching process is realized by exchanging optical carriers instead of payload signals, which does not degrade the signal power, guaranteeing the signal-to-noise ratio (SNR). We conducted a proof-of-concept experiment of 2 × 2 switching with two 1.2-GBaud quadrature phase-shift keying (QPSK) signals; an error vector magnitude (EVM) of or less than 13.87% is realized after forwarding. The proposed system has the advantages of low PC, high SNR, and fine granularity, and is very promising for flexible forwarding in future satcom systems.

Broadband 32 × 32 Strictly‐Nonblocking Optical Switch on a Multi‐Layer Si3N4‐on‐SOI Platform

AbstractLarge‐scale silicon optical switches are essential to support the ever‐increasing data traffic. Among the various switching architectures, the well‐known switch‐and‐select (S&S) architecture has the advantages of low crosstalk and strict non‐blocking. However, it suffers from high path‐dependent losses as the waveguide crossings increase dramatically with the number of ports. In this paper, a large‐scale 32 × 32 S&S optical switch on a multi‐layer Si3N4‐on‐SOI platform is reported. The optical switch chip incorporates 1984 broadband thermo‐optic Mach‐Zehnder interferometer (MZI)‐based switch elements, 246 016 three‐dimensional (3D) waveguide crossings, and 2048 interlayer couplers. Both ≈1‐mdB‐loss 3D waveguide crossings and ≈0.3‐dB‐loss interlayer couplers are realized, significantly reducing the overall insertion loss and footprint of the switch chip. The measured average fiber‐to‐fiber insertion loss is 12.88 dB at the 1580 nm wavelength. In addition, the crosstalk is less than −20.7 dB over the 110‐nm wavelength range. The power consumption of the entire switch chip is only ≈0.98 W due to the air trenches and substrate undercut. High‐fidelity optical transmission of a 50 Gb s−1 quadrature phase‐shift keying signal verifies the high‐performance routing capability of this chip. These results indicate that the large‐scale optical switch with broadband, low crosstalk, and high‐power efficiency is promising for datacenter optical network applications.

Performance Analysis of Scalable Optical Circuit Switch Employing Fast-Tunable AMZI Filters for Coherent Detection

High-port-count optical switches are expected to resolve the envisaged bandwidth and power crunch in intra-data center networks stemming from the slowdown of Moore's Law. This paper briefly reviews electrical switching technologies in current intra-data centers and discusses requirements for optical circuit switches in future data centers. We highlight an optical switch architecture that combines the two independent dimensions of space and wavelength to realize large port counts and fast switching. Wavelength routing is implementable with receiver-side channel selection using wavelength tunable filters (TFs). Coherent detection necessitates a fast-tunable local oscillator (LO) at the receiver. It can be cost-effectively realized using an LO bank that consists of fixed-wavelength laser sources and Silicon-photonic asymmetric Mach-Zehnder interferometer (AMZI) filters. Colorless detection that removes a TF at the front of the receiver is possible when the number of wavelength-division multiplexing (WDM) channels is small, however, as the number exceeds a certain limit the TF is needed to prevent power saturation of the receiver. We present an effective cooperative filtering scheme for transmission signals and LO channels sourced from an LO bank; it can detect C-band WDM coherent signals while easing the receiver's power limitation. The scheme is analyzed to clarify receiver performance and the switch port-count bounds under various operating conditions. We demonstrate that the cooperative filtering scheme effectively works from 60 (typical of coherent receivers) to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$ &gt; $</tex-math></inline-formula> 116 wavelength channels, which is verified by experiments for 1,856 × 1,856 optical switching with the short switching time of 3.2 μs.

Real-time transponder architecture for hitless transmission baud rate switching in association with an auto-negotiation protocol

We propose a novel digital signal processing architecture for a coherent receiver that allows instantaneous and hitless variable baud rate transmission for integer sub-division values. This solution allows the receiver to self-adapt a new baud rate without processing modification, re-initialization, or any knowledge of the transmission speed modification. As for implantation concern, this architecture requires negligible extra logic compared to the standard one. Its development and operation developed on a simulation basis are presented; then its dynamic behavior and performance are demonstrated in a real-time experiment attesting a zero-bit loss. We also show how an in-line auto-negotiation protocol between a transmitter and a receiver minimizing the mediation through the control plane can leverage this instantaneous baud rate variation.

N譔 Clos Digital Cross-Connect Switch Using Quantum Dot Cellular Automata (QCA)

Quantum dot cellular automata (QCA) technology is emerging as a future technology which designs the digital circuits at quantum levels. The technology has gained popularity in terms of designing digital circuits, which occupy very less area and less power dissipation in comparison to the present complementary metal oxide semiconductor (CMOS) technology. For designing the routers at quantum levels with non-blocking capabilities various multi-stage networks have been proposed. This manuscript presents the design of the N×N Clos switch matrix as a multistage interconnecting network using quantum-dot cellular automata technology. The design of the Clos switch matrix presented in the article uses three input majority gates (MG). To design the 4 × 4 Clos switch matrix, a basic 2 × 2 switch architecture has been proposed as a basic module. The 2 × 2 switching matrix (SM) design presented in the manuscript utilizes three input majority gates. Also, the 2 × 2 SM has been proposed using five input majority gates. Two different approaches (1&2) have been presented for designing 2 × 2 SM using five input majority gates. The 2 × 2 SM design based on three input majority gate utilizes four zone clocking scheme to allow signal transmission. Although, the clocking scheme used in 2 × 2 SM using three input MG and in 2 × 2 SM approach 1 using five input MG is conventional. The 2 × 2 SM approach 2 design, utilizes the clocking scheme in which clocks can be applied by electric field generators easily and in turn the switch element becomes physically realizable. The simulation results conclude that the 2 × 2 SM is suitable for designing a 4 × 4 Clos network. A higher order of input-output switching matrix, supporting more number of users can utilize the proposed designs.

A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices

The Dynamic Ranking Push-In-First-Out (DR-PIFO) is a novel programmable hardware queue architecture, introduced for the widely-used Portable Switch Architecture (PSA) used in modern network switches and routers. With the aid of a re-ranking mechanism, the DR-PIFO offers a flexible and expressive solution for a wide range of scheduling algorithms while still meeting line rate requirements. Our design, synthesized using TSMC’s 65nm technology, achieves the desired timing rate of 1GHz, while maintaining a throughput that matches the fastest existing schedulers while incurring a mere 15.5% increase in area compared to the state-of-the-art PIFO design. The proposed DR-PIFO’s hardware implementation is shown to closely approach the behavior and performance of its algorithmic model by efficiently executing various scheduling algorithms, leading to precise bandwidth distribution among traffic flows. Additionally, the DR-PIFO offers a significant reduction in the relative flow completion time (FCT) errors when implementing various scheduling policies with workloads collected from data centers. Thus, we believe that the DR-PIFO is a significant step toward making hardware packet schedulers more programmable.