Surface Potential Fluctuations Research Articles

Low-Frequency Noise Characteristics in Ion-Implanted GaN-Based HEMTs

Low-frequency noise characteristics in ion-implanted GaN/AlGaN/GaN and AlGaN/GaN HEMTs were investigated. The normalized spectral noise density was about 6 dB lower in GaN/AlGaN/GaN HEMTs than in AlGaN/GaN HEMTs. The normalized spectral noise density dependence on the gate length Lg indicates that the main origin of low-frequency noise is at the region under the gate in both devices. The Hooge parameters alphaH for both devices are on the order of 10-1-10- 2. The ion implantation process introduces a lot of defects in the source/drain regions, but the values of alphaH are comparable with those for conventional GaN-based HEMT devices. The values of alphaH are also lower in GaN/AlGaN/GaN HEMTs than in AlGaN/GaN HEMTs, which is due to the decrease of surface potential fluctuations in GaN/AlGaN/GaN HEMTs.

Evidence of low interface trap density in GeO2∕Ge metal-oxide-semiconductor structures fabricated by thermal oxidation

We have fabricated GeO2∕Ge metal-oxide-semiconductor (MOS) structures by direct thermal oxidation of Ge substrates. The interface trap density (Dit) of Al∕GeO2∕Ge MOS structures, measured by the low temperature conductance method including the effect of the surface potential fluctuation, is found to be reduced as the oxidation temperature increases. The minimum values of Dit can be obtained for the oxidation around 575°C, which is in the maximum temperature range where GeO volatilization does not occur under atmospheric pressure of O2. It is also found that the hydrogen annealing before Al gate formation is effective for the passivation of GeO2∕Ge interface states. It is clarified, as a result, that the minimum Dit value lower than 1011cm−2eV−1 can be obtained for GeO2∕Ge MOS interfaces fabricated by direct oxidation of Ge substrates.

Fluctuation of semiconductor surface potential in Si-SiO2 structure after irradiation and subsequent annealing

Fluctuations of the semiconductor surface potential in a Si-SiO2 structure, caused by irradiation with different high-energy particles (50 MeV electrons and 40 keV arsenic ions) and subsequent annealing, have been studied by measuring the semiconductor interface state parameters. It is established that the fluctuation of the semiconductor surface potential decreases slightly, from 0.049 V to 0.044 V, after irradiation, while a considerable increase is observed after annealing. For the samples irradiated by arsenic ions, the increase in fluctuation is much larger (0.096 V) than that for the electron-irradiated samples (0.06 V).

Analyzing conductance-frequency curves of metal-insulator-semiconductor structures subject to surface-potential fluctuations and electrically active states inside the insulator

For metal-insulator-semiconductor structures, a technique is described of analyzing the normalized conductance measured as a function of frequency with regard to the random variation of surface potential and the presence of electrically active states inside the insulator. Parameters are selected that are to be used in evaluating the amount by which the conductance-frequency characteristic is broadened. Analytical expressions are derived for the parameters. A method is proposed for separating the respective contributions of the tunneling and fluctuation mechanisms of the broadening. It enables one to evaluate the depth of the electrically active states and the variance of the surface potential when the two factors make comparable contributions to the inhomogeneity of the insulator-semiconductor interface.

Role of germanium nitride interfacial layers in HfO2/germanium nitride/germanium metal-insulator-semiconductor structures

The authors investigate the electrical properties of germanium nitride interfacial layers for germanium metal-insulator-semiconductor (Ge MIS) structures with HfO2 high-k dielectrics. A pure Ge nitride interfacial layer is fabricated by direct nitridation of a Ge substrate with the plasma processing before high-k deposition. The interface trap density of Au∕HfO2∕Ge niride/Ge MIS structures measured by the ac conductance method including the effect of the surface potential fluctuation is found to be as low as 1.8×1011cm−2eV−1 at the minimum. It is also found that Ge nitride interfacial layers mitigate the degradation of the accumulation capacitance during the high-temperature annealing.

Analysis of frequency dependences of conductance of MIS structures with the fluctuation-and tunneling-based theoretical models taken into account

A method for analyzing the frequency dependences of normalized conductance of MIS structures taking into account the effects of the surface-potential fluctuations and penetration of electrically active states deeper into the insulator is suggested. The parameters for estimating the broadening of the dependences are chosen. Analytic expressions for these parameters are derived. A method for separating the effects of the tunneling-and fluctuation-based mechanisms of broadening on the form of the conductance’s frequency dependence is suggested.

Application of Kelvin Probe Microscopy for Nitride Heterostructures

Kelvin probe microscopy is an experimental technique designed to investigate fluctuations of surface potential (work function per electron) related to distribution of electric charge or variations in composition. The paper describes principle and precision of measurements. The results obtained for group-III nitrides semiconductor heterostructures grown on c-plane sapphire by metal-organic vapour phase epitaxy are presented. The observations concerns defects: inversion domains for Gaand N-polar layers, threading dislocations and effects of spontaneous polarization leading to 2D carrier gas. To achieve insight in the evolution of defects, bevelled and cross-sectioned samples were investigated along with surface of “as grown” layers. Applicability of standard Kelvin probe microscopy method was also extended by investigating dependence of the surface potential on variable wavelength illumination, offering opportunity for spectroscopy of individual defects.

On the Si–SiO2 interface trap time constant distribution in metal-oxide-semiconductor transistors

The reliability of a charge pumping (CP) technique proposed recently, which allows the extraction of the Si–SiO2 interface trap concentration profiles in metal-oxide-semiconductor transistors, from fast to slow traps, is discussed. The shape of the trap concentration profiles measured, the values of the trap cross section extracted, and the integration of the trap profiles, which should give the interface trap density obtained using the conventional CP technique, are discussed with regard to the trap filling function variation and to surface-potential fluctuations. Then, the influence, on these profiles, of both carrier emission, which is neglected in the model used for calculating the profiles, and of the source and drain regions (S/D-R) of the devices, where the threshold and flatband voltages are different from those in the central region of the channel, is investigated. It is shown that carrier emission does not impact on the trap profiles and that the trap time constant distribution measured does not originate from the S/D-R of the devices. A way to detect a significant contribution of these regions to the charge pumping current measured is proposed. Finally, a comparison with noise spectroscopy is carried out. The results obtained using the two techniques agree very well.

Structural and surface potential characterization of annealed HfO2 and (HfO2)x(SiO2)1-x films

The evolution of the microscopic electrical properties of hafnium oxide and hafnium silicate films with high temperature anneals and their relationship to morphological changes is reported. The as-grown, amorphous 3nm thick HfO2 and 2.2nm thick Hf0.78Si0.22O2 layers were deposited ex situ on Si(100) by atomic layer deposition and metal organic vapor deposition, respectively, and annealed in situ in ultra high vacuum. A noncontact atomic force microscope operating in the electrostatic force mode was used to image the topography, contact potential difference (CPD), and differential capacitance. The as-grown and annealed films essentially retained their smoothness even after undergoing crystallization; rms roughness of ∼0.13nm for HfO2 and 0.077nm for the 900°C annealed Hf0.78Si0.22O2 layer were measured. These values compare favorably with state-of-the-art rapid thermal oxidation and nitrided SiO2 gate oxides. CPD or surface potential fluctuations of up to 0.3–0.4V were observed in images of area 200×200nm2; values that did not change appreciably with annealing. A lack of correlation between topographic and CPD image features for the as-grown amorphous samples changed dramatically once the films crystallized, with higher CPD values associated with grain boundaries for both oxide and silicate layers. CPD variations were about a factor of 2 larger than for SiO2 gate oxides. Differential capacitance images reflected mainly topographic surface features, as the high κ inhibits image contrast in the images for small to moderate changes in κ. Nevertheless, for the Hf0.78Si0.22O2 sample annealed at 900°C, which exhibited the lowest roughness, increase in differential capacitance could be attributed to microstructures of high-κ material, most likely HfO2, which phase separated during the anneal. Because of screening, the high κ dielectric also tends to suppress contributions of isolated charges to the CPD image. A spherical tip model is presented that supports these observations.

Characterizations of SiC/SiO<sub>2</sub> Interface Quality Toward High Power MOSFETs Realization

The low channel mobility in N-MOS 4H-SiC transistor is a major key issue for the development of power devices with satisfactory on state characteristics. Previous works have demonstrated that this low channel mobility is due to high interface state density (Dit) near the conduction band edge. Furthermore, the realization of SiC MOSFETs sustaining high reverse field necessitates thick epitaxial layer growth. An important thickness (> 30 gm) unfortunately involves important surface roughness which may result in a high interface trap density (Dit) and surface potential fluctuation (sigma(s)) at the SiC/SiO2 interface. In this study, we focus on SiO2/SiC MOS interface quality characterization as a function of process conditions and material properties (dopant type, thick layer growth technique). Investigations of the oxide quality on thick layers grown by CVD and PVT has been realized using CV under UV lightening and GV techniques. We evidenced that the Dit value (between 10(10) cm(-2).eV(-1) and 9x10(10) cm(-2).eV(-1) from 0.9 Ev to 0.2 eV below Ec) and sigma(s) value (60 mV) were slightly lower for thick PVT layers. A discrepancy in the Dit values obtained from C-V and G-V measurements is attributed to the large surface potential standard deviation. Results from an original oxide growth process using a deposited sacrificial silicon layer under UHV conditions are also presented.

Unpassivated GaN/AlGaN/GaN power high electron mobility transistors with dispersion controlled by epitaxial layer design

In this paper, a novel GaN/AlGaN/GaN high electron mobility transistor (HEMT) is discussed. The device uses a thick GaN-cap layer (∼250 nm) to reduce the effect of surface potential fluctuations on device performance. Devices without Si3N4 passivation showed no dispersion with 200-ns-pulse-width gate-lag measurements. Saturated output-power density of 3.4 W/mm and peak power-added efficiency (PAE) of 32% at 10 GHz (VDS=+15 V) were achieved from unpassivated devices on sapphire substrates. Large gate-leakage current and low breakdown voltage prevented higher drain-bias operation and are currently under investigation.

Interface structure of ultrathin oxide prepared by N/sub 2/O oxidation

With X-ray photoelectron spectroscopy (XPS) measurements, we found in the N/sub 2/O-grown oxide that the nitrogen incorporation should involve the NO or N reaction with the Si-Si bond and P/sub b/ centers at the interface. Consequently, nitrogen content is very low and accumulated mainly at the interface. In addition, we found that the nitrogen atoms at the interface exist in the form of Si-N bonding and the interface oxynitride layer is a mixture of SiO/sub 2/ and Si/sub 3/N/sub 4/ clusters. This structure will result in several undesirable effects. It will give rise to the permittivity and bandgap fluctuations at the interface and hence induced gigantic surface potential fluctuation and mobility degradation in the channel of MOS devices. This bonding structure also explains the interface trap generation during the electrical stressing. The sources of trap generation are attributed to the Si-Si bonds, P/sub b/ centers, and nitride-related defects due to the over-constrained silicon atoms in the Si/sub 3/N/sub 4/ clusters at the interface.

P-capped GaN-AlGaN-GaN high-electron mobility transistors (HEMTs)

A novel p-capped GaN-AlGaN-GaN high-electron mobility transistor has been developed to minimize radio-frequency-to-dc (RF-DC) dispersion before passivation. The novel device uses a p-GaN cap layer to screen the channel from surface potential fluctuations. A low-power reactive ion etching gate recess combined with angle evaporation of the gate metal has been used to prevent gate extension and maintain breakdown voltage. Devices with gate lengths of 0.7 μm have been produced on sapphire. Current-gain cutoff frequencies (f/sub /spl tau//) of 20 GHz and maximum frequencies of oscillation (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) of 38 GHz have been achieved. Unpassivated devices demonstrated a saturated output power of 3.0 W/mm and peak power-added efficiency of 40% at 4.2 GHz (V/sub DS/ = +20 V).

Characterisation of charge trapping at the Si–SiO 2 (100) interface using high-temperature conductance spectroscopy

We report an experimental study of interface silicon trivalent defects on (100) oriented MOS structures. Considering the surface potential fluctuations, high-temperature conductance spectroscopy is used to detect acceptor and donor trap energy levels on N- and P-type devices, respectively, and to measure their capture cross-sections. The trap levels values are confirmed by a UV-assisted capacitance analysis. The capture cross-sections show very good agreement with published data deduced from different experimental methods. Our results confirm the capability of high-temperature conductance spectroscopy for interface defects characterisation.

Interconnect and Substrate Structure for Gigascale Integration

Signal wave propagation properties for a high-speed gigascale integration (GSI) system LSI featuring an operation frequency of more than 10 GHz have been analyzed and discussed by solving the cylindrical Maxwell's equations directly using a stacked coaxial structure. The results give us a good perspective and enable us to predict the ultrahigh-speed and miniaturized interconnect characteristics. The metal substrate structure is essential to suppress the substrate surface potential fluctuations and the substrate-induced signal attenuation and delay. The gas-isolated interconnect structure can effectively reduce the signal attenuation and delay. The combination of the gas-isolated interconnect and the metal substrate structure is the most promising solution for an interconnect and a substrate in GSI.

High-quality oxide/nitride/oxide gate insulator for GaN MIS structures

We report on a SiO/sub 2//Si/sub 3/N/sub 4//SiO/sub 2/ (ONO) gate insulator stack deposited on GaN by jet vapor deposition (JVD) technique. Capacitors fabricated using the JVD-ONO on GaN are characterized from room temperature to 450/spl deg/C using capacitance-voltage (C-V), current-voltage (I-V), AC conductance, and constant-current stress measurements. We find excellent operating characteristics over the measured range, most notably: (1) very low leakage current, (2) extremely high hard-breakdown strength, (3) low interface-trap density, and (4) low net dielectric-charge density. Moreover these performance figures remain well within acceptable limits even for operating temperatures as high as 150/spl deg/C. In addition, we measure both the capture cross-section of the interface traps and the surface-potential fluctuation at the GaN/ONO interface. All results suggest that JVD-ONO is an excellent choice for a gate dielectric in GaN-based MISFETs.

Simulation and correction of geometric distortions in scanning Kelvin probe microscopy

Capacitance due to geometric influence of the finite tip shape and influence of distant surface points can lead to artifacts in scanning Kelvin probe microscopy (SKPM) images. These artifacts appear as features in the SKPM image which are due only to tip/surface geometry and not to true surface potential variations. They can also cause blurring of real features. Such effects are most prominent for samples with rich topography. We present here a method for identifying and removing these artifacts, and demonstrate it for a gold sample with rich topography relative to the nearly flat surface potential fluctuations.

Light scattering from slightly rough semiconductor surfaces near exciton resonance

The phenomenon of light scattering by a randomly rough surface and fluctuations of the excitonic surface potential is investigated by means of a first-order perturbation theory. We employ the generalized Morse potential to describe both intrinsic (repulsive) potentials and extrinsic near-surface potential wells. Frequency and angle dependencies of the light-scattering cross section are calculated. A considerable increase of the scattering cross section, as the correlation between the surface roughness and the excitonic potential fluctuations diminishes, is observed. Our theory describes very well available experimental results for samples with a repulsive surface potential. Also, the optical manifestation of excitonic bound states, generated within a surface-potential well, is analyzed. We find that the near-surface localized excitons produce a resonance structure in the spectrum of the light-scattering cross section, which is very sensitive to the degree of correlation between surface roughness and potential-well fluctuations.

Photoinduced noise amplification in semiconductor structures

To explain the noise amplification found experimentally in semiconductor structures under optical illumination, a physical model of this phenomenon has been considered for which the spectral power density of the surface potential fluctuations in the Schottky diodes and MIS structures has been calculated. Procedures for measuring low-level noise in a semiconductor structure have been proposed with its integral illumination and scanning of the surface of the structure with an optical beam to detect the positions of noise sources.

Analysis of the standard deviation of surface potential fluctuations in MOS interface from DLTS spectra

The surface potential fluctuations can have significant effects on both the magnitude and shape of the measured small-pulse DLTS spectrum. An increase in the dispersion parameter of the surface potential distribution, which is assumed to have a Gaussian form, leads to a reduction in the DLTS signal size, a shift of the peak position and a broadening of the peak shape. A computer program including the exponential temperature dependence of hole capture cross section, , was developed to analyse temperature-scan DLTS spectra of a MOS structure; in the evaluation procedure , and are taken as fitting parameters. A bias dependence of has been found and an interpretation of this behaviour has been attempted in the light of random point charges (Brews) and patchwork (Nicollian-Goetzberger) models.