Surface Mount Technology Research Articles

Electronic module assembly

Electronics is the vital basis for innovations and the essential enabler for global trends like connectivity, electro mobility and renewable energies. These applications require high performance and reliability of the electronic modules. Their assembly combines very heterogeneous process chains like remarkable productive and diminutive surface mount technology (SMT), powerful and robust power electronic interconnection techniques, as well as pioneering reel-to-reel based organic electronic printing. After briefly outlining the enormous global economic impact of electronic modules, this paper presents the state of the art of electronic module assembly including substrate materials, electronic components, packaging and assembly processes as well as quality and reliability testing methods.

A Guided Evolutionary Search Approach for Real-Time Stencil Printing Optimization

This study aims to identify and maintain optimal stencil printer settings in dynamic surface mount technology (SMT) assembly lines to control the solder paste volume transfer efficiency (TE) and increase the yield rates of surface mount assembly (SMA) lines. Stencil printing process (SPP) is a crucial procedure that determines the first pass yields in SMA lines. Stencil printing speed (PS) and printing pressure (PP) are two critical SPP parameters in the manufacturing process; identifying the optimal printer settings in complex fabrication environment is cost efficient but challenging. To search for the global optimal PS and PP values in real time with minimal computational efforts, a dynamic optimization SPP optimization system is proposed based on a novel guided evolutionary search (GES) strategy. The GES algorithm is flexible to adjust the feasible solution region based on real-time optimization results to maximize the probability of finding optimal solutions and minimize the computational burden. As a major extension on the classical evolutionary search, the GES minimizes the possibility to fall in the local optimal due to insufficiencies in the prediction accuracy and guarantees global optimality within the dynamically varying printing environment.

Printed Circuit Board Assembly Planning for Multi-Head Gantry SMT Machine Using Multi-Swarm and Discrete Firefly Algorithm

This research proposes a Multi-swarm and Discrete Firefly Algorithm (MDFA) to deal with the component sequencing problem (CSP) and feeder assignment problem (FAP) simultaneously for a multi-head gantry surface-mounted technology (SMT) machine. The MDFA is an improved version of standard Firefly Algorithm (FA) which is a kind of nature-inspired and population-based metaheuristic. To our best knowledge, the FA has never been used to deal with the CSP and FAP simultaneously for the multi-head gantry SMT machine. Empowered by novel features such as multiple swarms as well as adaptive and discrete moving step, in addition to using an exploration-to-exploitation strategy, the MDFA is found capable of searching a solution space effectively. To investigate its effectiveness, the MDFA has been compared to the standard FA, particle swarm optimization (PSO), and genetic algorithm (GA). The experimental results show that the MDFA outperforms the others in terms of assembly time.

PRZEGLĄD WYKORZYSTANIA AOI W PROCESIE KONTROLI MONTAŻU POWIERZCHNIOWEGO

Technologia montażu powierzchniowego jest obecnie szeroko stosowana w produkcji zespołów obwodów drukowanych w przemyśle elektronicznym. Zyskała ona bardzo wielu zwolenników. Miniaturyzacja komponentów elektronicznych wymusiła wprowadzenie maszyn wizualnej kontroli poprawności montażu, bardziej dokładnych i szybszych niż ludzkie oko, lupa czy mikroskop. Automatyczna Inspekcja Optyczna (AOI) to proces kontroli wykrywania wad i błędów w początkowym procesie produkcji obwodów drukowanych. Staje się nieodzownym elementem montażu kontraktowego, wpływając na zwiększenie jakości oferowanych usług i efektywności produkcji. Wykorzystywane są w niej nowe konstrukcje głowic pomiarowych, miniaturyzacja sprzętu, oprogramowanie przetwarzące otrzymane obrazy płytek, skomplikowane algorytmy przekształcania obrazu.

Convolutional Recurrent Reconstructive Network for Spatiotemporal Anomaly Detection in Solder Paste Inspection.

Surface mount technology (SMT) is a process for producing printed-circuit boards. The solder paste printer (SPP), package mounter, and solder reflow oven are used for SMT. The board on which the solder paste is deposited from the SPP is monitored by the solder paste inspector (SPI). If SPP malfunctions due to the printer defects, the SPP produces defective products, and then abnormal patterns are detected by SPI. In this article, we propose a convolutional recurrent reconstructive network (CRRN), which decomposes the anomaly patterns generated by the printer defects, from SPI data. CRRN learns only normal data and detects the anomaly pattern through the reconstruction error. CRRN consists of a spatial encoder (S-Encoder), a spatiotemporal encoder and decoder (ST-Encoder-Decoder), and a spatial decoder (S-Decoder). The ST-Encoder-Decoder consists of multiple convolutional spatiotemporal memories (CSTMs) with a spatiotemporal attention (ST-Attention) mechanism. CSTM is developed to extract spatiotemporal patterns efficiently. In addition, an ST-Attention mechanism is designed to facilitate transmitting information from the spatiotemporal encoder to the spatiotemporal decoder, which can solve the long-term dependency problem. We demonstrate that the proposed CRRN outperforms the other conventional models in anomaly detection. Moreover, we show the discriminative power of the anomaly map decomposed by the proposed CRRN through the printer defect classification.

First Principles Statistical Process Monitoring of High-Dimensional Industrial Microelectronics Assembly Processes

Modern industrial units collect large amounts of process data based on which advanced process monitoring algorithms continuously assess the status of operations. As an integral part of the development of such algorithms, a reference dataset representative of normal operating conditions is required to evaluate the stability of the process and, after confirming that it is stable, to calibrate a monitoring procedure, i.e., estimate the reference model and set the control limits for the monitoring statistics. The basic assumption is that all relevant “common causes” of variation appear well represented in this reference dataset (using the terminology adopted by the founding father of process monitoring, Walter A. Shewhart). Otherwise, false alarms will inevitably occur during the implementation of the monitoring scheme. However, we argue and demonstrate in this article, that this assumption is often not met in modern industrial systems. Therefore, we introduce a new approach based on the rigorous mechanistic modeling of the dominant modes of common cause variation and the use of stochastic computational simulations to enrich the historical dataset with augmented data representing a comprehensive coverage of the actual operational space. We show how to compute the monitoring statistics and set their control limits, as well as to conduct fault diagnosis when an abnormal event is declared. The proposed method, called AGV (Artificial Generation of common cause Variability) is applied to a Surface Mount Technology (SMT) production line of Bosch Car Multimedia, where more than 17 thousand product variables are simultaneously monitored.

Analysis of Defects Generated by the Reflow Soldering in SMT (Surface Mount Technology) Assembly Applying the Six Sigma Method

The Six Sigma method using the DMAIC methodology is being applied for analyzing the reflow soldering process in an SMT assembly line. The Define phase (D) and Measure phase (M) were concluded, the Analysis (A) phase is being implemented, and the Improve (I) and Control (C) phases will be the next ones. Defects generated during the reflow process were classified and measured both on assembled memory modules and on virgin laminates that were passed through the oven during the reflow of these modules. Spots of solder and flux were found on the edge connector of the modules and also on the surface of the virgin laminates. It was found that these defects are generated inside the reflow oven, indicating that the oven is contaminated. Two solder pastes were analyzed and consequently, two temperature profiles were used. The amount of defects generated by the oven was found to be independent on the temperature profile. On the other hand the amount of defects depends on the solder paste that is used. The FMEA (Failure Mode and Effect Analysis) was also accomplished. As a result, the main failure modes of the reflow process were determined, namely, the heating rate, the soak temperature, the conveyor velocity, the reflow temperature, the reflow time, and the cooling rate.

Predicting the printed circuit board cycle time of surface-mount-technology production lines using a symbiotic organism search-based support vector regression ensemble

This paper presents a symbiotic organism search (SOS)-based support vector regression (SVR) ensemble for predicting the printed circuit board (PCB) cycle time of surface-mount-technology (SMT) production lines. Being able to predict the PCB cycle time accurately is essential for optimising the SMT production schedule. Although a machine simulator can be reliably used for single-type PCB production, it is time-consuming and often inaccurate for the simulator to be applied for highly mixed orders in multiple flexible SMT production lines. Due to the dynamic changes in both PCB orders and SMT production lines, there is a diverse set of samples, but the size of similar samples is relatively small. An SVR model is therefore used to estimate the PCB cycle time, and the SOS algorithm is employed to optimise the SVR parameters. We assume that uncertainties during the assembly process can be captured by the characteristics of PCB and SMT lines, which are utilised as features to train the SVR model. To enhance the performance of the prediction accuracy, an SOS-SVR ensemble is proposed. Experiments based on datasets collected from a leading global electronics manufacturer confirm the efficiency of the proposed approach compared to industrial solutions currently in place and other machine learning methods.

Adaptive 5G Architecture for an mmWave Antenna Front-End Package Consisting of Tunable Matching Network and Surface-Mount Technology

Adaptive 5G architecture consisting of three functional sections (four antenna components, tunable matching network (TMN), and radio frequency (RF) front-end package) is proposed, analyzed, and verified. In the 5G millimeter-wave (mmWave) spectrum, the RF performance is highly dependent on the specific antenna package technology. However, compact antenna packages, oftentimes, result in undesired interference between the antenna elements. This eventually leads to severe RF performance degradation. For the first time in the literature, an mmWave 5G RFIC and the TMN are integrated for efficient operation that is applicable to real-life 5G mobile devices. Moreover, the proposed antenna-in-package (AiP) architecture enables independent frequency control at multiple frequencies. The proposed solution is simulated and measured at the system level. As a result, the devised AiP solution exhibits a simulated effective isotropic radiated power (EIRP) of 22.05–23.96 dBm at the cumulative distribution function (CDF) of 50% by applying the conducted power of 17 dBm (per channel), and the peak gain of the antenna exhibits 13.7 dBi at 27 GHz (state A) and 12.6 dBi at 28 GHz (state B) with an amplifier having an output power of 5 dBm.

Surface Mount Technology for Silica-Based Planar Lightwave Circuit and Its Application to Compact 16×16 Multicast Switch

We demonstrated a compact 16×16 multicast switch (MCS) made from a silica-based planar lightwave circuit (PLC). The switch utilizes a new electrical connection method based on surface mount technology (SMT). Five electrical connectors are soldered directly to the PLC by using the standard reflow process used for electrical devices. We reduced the chip size to half of one made with conventional wire bonding technology. We obtained satisfactory solder contacts and excellent switching properties. These results indicate that the proposed method is suitable for large-scale optical switches including MCSs, variable optical attenuators, dispersion compensators, and so on.

Free standing tapes of donor doped BaTiO3 for multilayer positive temperature coefficient thermistors

A disruptive method of fabricating free-standing tapes of La-doped (BaCaSrPb)TiO 3 thermistors is demonstrated. The greatest advantage is that the free-standing tapes do not require high temperature co-firing of electrodes or reduced environment cofiring — soft oxidation cycle to obtain thermal sensitivity. The approach thus solves the long-standing problem with the ceramic thermistor technology that eluded its compatibility with surface mount technology (SMT) and miniaturization. Stencil printing is employed that can fabricate up to 500 μm thick tapes in a single step, saving huge cost and processing steps for application requiring thicker films. The pastes suitable for freestanding tapes are reported. The method provides a novel route to integrate PTC elements into the chips of passive components and would lead to a massive reduction in cold resistivity when developed in multilayer laminated stacks.

Free standing tapes of donor doped BaTiO3 for multilayer positive temperature coefficient thermistors

A disruptive method of fabricating free-standing tapes of La-doped (BaCaSrPb)TiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> thermistors is demonstrated. The greatest advantage is that the free-standing tapes do not require high temperature co-firing of electrodes or reduced environment cofiring — soft oxidation cycle to obtain thermal sensitivity. The approach thus solves the long-standing problem with the ceramic thermistor technology that eluded its compatibility with surface mount technology (SMT) and miniaturization. Stencil printing is employed that can fabricate up to 500 μm thick tapes in a single step, saving huge cost and processing steps for application requiring thicker films. The pastes suitable for freestanding tapes are reported. The method provides a novel route to integrate PTC elements into the chips of passive components and would lead to a massive reduction in cold resistivity when developed in multilayer laminated stacks.

Effect of Temperature on Solder Paste During Surface Mount Technology Printing

There are lots of companies manufacturing electronic components that have commonly used the Surface Mount Technology printing process. However, the temperature of solder paste printing on the Printed Circuit Board can influence the presence of defects in Surface Mount Technology. In this paper, the experiment called Surface Mount Technology printing is built and tested to characterize the temperature of solder pastes in order to prevent the electronic waste and rejection rate of the malfunctioning electronics due to poor soldering. The microstructures of solder paste on printed circuit board and copper substrate are inspected under Scanning Electron Microscopy. It is focused on two parameters that affect the performance of a printed circuit board, which includes the filling areas of solder paste and the distance between ball grid arrays. From the experiment and analysis results, the filling area decreases as the temperature increases during the Surface Mount Technology printing process. In short, when the temperature of SAC305 increases, the viscosity and filling areas decreases. In fact, SAC305 gave the second rank of smallest area (18.86%) and distance (43.43%) after SAC307. The average area and distance are fair enough for the solder to hold the component placement, unlike SAC307 which likely causes tombstone.

Residue buildup predictive modeling for stencil cleaning profile decision-making using recurrent neural network

This research proposes a novel framework to control the stencil cleaning profile selection in the stencil printing process (SPP). The SPP is a major contributor to yield loss in surface mount technology (SMT). Enhancement in SPP performance is critical to improving the printed circuit board (PCB) assembly line. The selection of a solvent-based or a dry-based cleaning profile is challenging, but the choice determines the effectiveness and efficiency of the stencil cleaning operation. The amount of residue buildup under the stencil is the main criterion used to decide the appropriate cleaning profile in SPP. In this research, a multi-dimensional temporal recurrent neural network (RNN) approach is used to accurately predict the amount of residue buildup on the underneath surface of the stencil in real-time. Specifically, the long short-term memory (LSTM) architecture is trained using actual residue buildup data. The proposed LSTM prediction model is compared with other state-of-the-art regression models such as multilayer perceptron (MLP) and ensemble learning models. Experimental results show the proposed LSTM model outperforms the state-of-the-art regression models and accurately predicts the stencil status. The proposed research aids decision-makers in the SPP line to select the appropriate stencil cleaning profile adaptively and in real-time. As a result, the overall SPP performance is improved.

Applied Research of Hierarchical Multi-objective Optimization Method in High Speed and High Precision Placement Machine

In practical engineering, placement optimization of multi-head in the high speed and high precision Surface Mount Technology (SMT) is a multi-objective optimization problem. It mainly includes the feeder distribution optimization, the component placement sequence optimization and the nozzle configuration optimization. Optimization problems are complicated and mutual coupling between them. In this paper, the hierarchical multi-objective optimization model is developed. In the hierarchical structure, the nozzle optimization is constructed as a 0-1 integer programming optimization model for the first master hierarchy. In the second hierarchical, component mounting sequence, feeder optimization and picking order are parallel optimized based on the first hierarchy optimization. The respective problems related algorithm strategies have been proposed. The engineering experiments show that this hierarchical multi-objective optimization method can significantly improve the overall performance of the multi-head placement machine with high speed and high precision.

Fully convolutional networks for void segmentation in X-ray images of solder joints

Whether in sensory or illumination applications, optoelectronic components are an essential part of our everyday life. To actually include them in smartphones, cars or other products, they need to be soldered onto the surface of a printed circuit board via surface-mounted technology. Hereby, the solder joint is formed by remelting the solder paste that was printed onto the board before the optical component was mounted. During this process, the evaporating flux causes porosities (voids) filled with gas that is caught in the solidifying alloy. Voids influence the thermal and electric properties of a solder joint and hence reduce its reliability. Because the solder joint is embedded between the device and the board, non-destructive X-ray inspection is used to visualize voids. However, the superposition of various structures in a noisy image acquisition process renders the semantic segmentation of solder joints and voids in X-ray images difficult. To the best of our knowledge, there is no method for automatic void segmentation in flat solder joints based on X-ray images aside from this work. We develop a fully convolutional network for pixel-wise classification of X-ray images and show, how our contributions enable automatic void inspection of soldered structures without protracted X-ray tomography of flat samples, so-called laminography.

A Predictive Abnormality Detection Model Using Ensemble Learning in Stencil Printing Process

This article aims to propose a predictive abnormality detection model in the stencil printing process (SPP). The SPP is the main contributor to surface mounting technology (SMT) soldering defects. The prediction of abnormal conditions is necessary to enhance the first-pass yield and reduce the reworking costs of the printed circuit board (PCB) assembly line. In this research, a novel multiphase intelligent abnormality prognosis (IAP) framework is proposed. The model comprises two phases: the abnormality detection phase and the abnormality prediction phase. The first phase is to develop the random forest-based exponential weighted moving average (RF-based EWMA) control chart. The goal is to properly monitor the highly autocorrelated SPP process and effectively recognize the existing patterns. In the second phase, the accurate prediction of anomalies within the SPP before they arise is achieved. The integration of adaptive boosting (AdaBoost) predictive modeling and a moving recognition window approach is proposed. To discriminate the different patterns from each other, features are extracted using the sliding window, and then, the AdaBoost model is adopted to predict the occurrence of abnormal patterns in the SPP. The experimental results confirm the effectiveness and reliability of the proposed framework in early and accurate prediction of abnormal patterns within the SPP process to prevent solder paste printing defects and reduce the high reworking costs for large-scale production.

Automated fabrication of hybrid printed electronic circuits

Printed electronics offer great potential for new applications such as Internet of Things devices and wearables. However, to date, only a limited number of electronic functions and integration densities can be realised by printing processes. Hence, hybrid printed electronic circuits are actually created by mounting silicon electronic components. Since both printed materials and processes are continuously evolving, an accompanying structured development methodology is required. This paper highlights a digital workflow from design to automated fabrication using the example of a demonstrator circuit. A multi-layer vector ink-jet printing process to print electronic devices onto foil substrates with three functional inks is presented. This printing process is improved using a newly set-up printing system: Integrating a piezo print head into the path planning of the printing system and its control as a virtual stepper axis enable highly precise vector printing. This leads to printed resistors with low tolerances. Adaptations of surface mount technology for assembling silicon electronic components onto printed foil substrates are discussed. Finally, image processing methods to cope with deformations of the flexible foil substrates in the fabrication process are introduced.

ESD Diode Protection Incorporated on Leadframe Package

With the new die technology becomes smaller and thinner, silicon die circuit metallization also becomes smaller, thus electronic devices like quad-flat no-leads multi-row (QFN-mr) semiconductor leadframe package design become more sensitive and prone to electrostatic discharge (ESD) damages. This paper focused and introduced an additional surface mount technology by attaching diodes before and after diebonding process to protect the whole package and to prevent package related issues encountered. With this diode attached on the silicon die and leads, added protection could be achieved on the integrated circuit (IC) mounted on the circuit board level.

SMT Assembly Inspection Using Dual-Stream Convolutional Networks and Two Solder Regions

The automated optical inspection of a surface mount technology line inspects a printed circuit board for quality assurance, and subsequently classifies the chip assembly defects. However, it is difficult to improve the accuracy of previous defect classification methods using full chip component images with single-stream convolutional neural networks due to interference elements such as silk lines included in a printed circuit board image. This paper proposes a late-merge dual-stream convolutional neural network to increase the classification accuracy. Two solder regions are extracted from a printed circuit board image and are input to a convolutional neural network with a merge stage. A new convolutional neural network structure is then proposed that is able to classify for defects. Since defect features are concentrated in solder regions, the classification accuracy is increased. In addition, the network weight is reduced due to a reduction of the input data. Experimental results for the proposed method show a 5.3% higher performance in F1-score than a single-stream convolutional neural network based on full chip component images.