Suppression Of Boron Penetration Research Articles

A comprehensive study of suppression of boron penetration by amorphous-Si gate in P/sup +/-gate PMOS devices

This paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p/sup +/-gate devices. The characteristics and reliability for different gate structures (poly-Si, /spl alpha/-Si, poly-Si/poly-Si, poly-Si//spl alpha/-Si, /spl alpha/-Si/poly-Si, and /spl alpha/-Si//spl alpha/-Si) in p/sup +/ polygate PMOS devices are investigated in detail. The suppression of boron penetration by the nitrided gate oxide is also discussed. The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p/sup +/ polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate. Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance. The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p/sup +/-gate PMOS device for future dual-gate CMOS process. In addition, by employing a long time annealing at 600/spl deg/C prior to p/sup +/-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate. Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect.

Suppression of boron penetration in BF/sub 2/-implanted p-type gate MOSFET by trapping of fluorines in amorphous gate

This paper reports the use of amorphous/polysilicon gate electrode in BF/sub 2/-implanted poly-gated P-MOSFETs to suppress the boron penetration. SIMS analysis clearly illustrates that fluorine prefers to accumulate in the layer of amorphous silicon. The retardation of boron diffusion is therefore achieved by the trapping of fluorine in the amorphous layer of stacked amorphous/polysilicon (SAP) p-type gate due to a lower diffusion rate of fluorine in the amorphous silicon layer. Polysilicon depletion effect did not become more severe by introducing the amorphous silicon. In addition, gate oxide reliability is not degraded by using this gate structure. Results show that the structure is a promising gate electrode for future dual-poly gate CMOS technology development.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Electrical characteristics of rapid thermal nitrided-oxide gate n- and p-MOSFET's with less than 1 atom% nitrogen concentration

The characteristics and reliability of nitrided-oxide gate n- and p-MOSFET's with less than 1 atom% nitrogen concentration in the gate films were investigated in detail. These very light nitridations were accomplished using NH/sub 3/ gas at low temperatures/spl minus/from 800/spl deg/ C to 900/spl deg/ C. Nitrogen concentrations as low as 0.13 atom% were successfully measured by SIMS and AES. The region of optimum nitrogen concentration for deep-submicron devices is discussed. We explain how good drivability and good hot-carrier reliability were attained simultaneously with a nitrogen concentration of around 0.5 atom%, which is equivalent to that of oxynitride gate MOSFETs using N/sub 2/O gas. The suppression of boron penetration is also discussed. Light nitridation by ammonia gas is particularly desirable for deep-submicron processes because it can be accomplished at a relatively low temperature of about 900/spl deg/C.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Suppression of boron penetration in p/sup +/ polysilicon gate P-MOSFETs using low-temperature gate-oxide N/sub 2/O anneal

It has been reported that high-temperature (/spl sim/1100/spl deg/C) N/sub 2/O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900/spl sim/950/spl deg/C) N/sub 2/O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO/sub 2/ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60/spl sim/110 /spl Aring/ gate oxides, a certain amount of nitrogen (/spl sim/2.2%) incorporated near the Si/SiO/sub 2/ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Optimization of gate oxide N/sub 2/O anneal for CMOSFET's at room and cryogenic temperatures

This paper presents a study of the impact of gate-oxide N/sub 2/O anneal on CMOSFET's characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 /spl Aring/) and five N/sub 2/O anneal conditions (900/spl sim/950/spl deg/C, 5/spl sim/40 min) plus nonnitrided process and channel lengths from 0.2 to 2 /spl mu/m were studied to establish the correlation between the nitrogen concentration at Si/SiO/sub 2/ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N/sub 2/O anneal step can increase CMOSFET's lifetime by 4/spl sim/10 times, effectively suppress boron penetration from the P/sup +/ poly-Si gate of P-MOSFET's without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO/sub 2/ interface. The optimal N/sub 2/O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO/sub 2/ interface which can be realized by annealing 60/spl sim/110 /spl Aring/ oxides at 950/spl deg/C for 5 min or 900/spl deg/C for 20 min. >

The use of ultrathin reoxidized nitrided gate oxide for suppression of boron penetration in BF/sub 2//sup +/-implanted polysilicon gated p-MOSFETs

The authors report the use of rapid thermal reoxidized nitrided thin ( approximately 90-AA) gate oxides in BF/sub 2//sup +/-implanted polysilicon gated p-MOSFETs. Although lightly nitrided gate oxides are unable to block the boron penetration, reoxidized nitrided gate oxides are found to have excellent barrier properties against boron penetration. In addition, excellent electrical characteristics in terms of device subthreshold conduction and transconductance are illustrated. >