Suppression Of Boron Penetration Research Articles

Boron diffusion and activation in polysilicon multilayer films for P+ MOS structure: Characterization and modeling

This work deals with in situ boron diffusion and activation in multilayer films: polysilicon (Poly1)/amorphous silicon (Poly2). These films are deposited by LPCVD technique. However, several heat treatments were carried in order to determine the optimal annealing conditions to suppress boron penetration from the gate to the substrate through the gate oxide in MOS structure. The boron concentration is monitored by secondary ion mass spectrometry (SIMS). To investigate SIMS profiles we proposed a model of boron diffusion into these multilayer structures. It is important to note that the parameter values of the studied films such as the diffusion coefficient, the activation percentage of boron as well as the acceleration rate of boron diffusion are deduced from adjustment of simulated profiles with experimental profiles. From these results, we inferred that the boron is electrically active and its distribution does not reach the oxide layer and consequently, the Poly2 may reduce the boron diffusion in optimal annealing conditions.

Effects of film reoxidation on the growth and material properties of ultrathin dielectrics grown by rapid thermal nitridation in ammonia

Ultrathin silicon oxynitrides have been used successfully as gate dielectrics for advanced complementary metal-oxide semiconductor technologies. Here, the authors compare the growth and material properties of oxynitrides grown by rapid thermal nitridation of silicon in ammonia (RT-NH3) followed by reoxidation in NO, O2, or N2O. While the nitrogen concentration of the film is primarily determined by the RT-NH3 condition, reoxidation causes a slight change in nitrogen content and increase in film thickness which varies depending on the initial nitrogen concentration in the film and the oxidizing conditions used. The nitrogen/oxygen concentration ratio was determined to be sensitive to the reoxidizing species, process pressure, and exposure time. Compositional analysis by medium energy ion scattering indicates similarities in microstructure but differences in nitrogen and oxygen profiles among the different films. Results indicate that reoxidation in NO, O2, or N2O can result in different nitrogen concentrations at the bottom interface under the same process conditions. Thus, the choice of reoxidizing species may be an important decision for a gate dielectric process since the amount and placement of nitrogen needs to be optimized to reduce the impact on device peak mobility and threshold voltage, while still be sufficient to improve hot carrier reliability, reduce defect generation rates and gate leakage current, and suppress boron penetration from the gate electrode [D. A. Buchanan, IBM J. Res. Dev. 43, 245 (1999); M. L. Green et al., J. Appl. Phys. 90, 205 (2001); E. Gusev et al., IBM J. Res. Dev. 43, 265 (1999)].

P형 in-situ 도핑 폴리실리콘 막질에 관한 연구

This paper reports physical properties of in situ boron doped silicon films made from boron source gas and silane (<TEX>$SiH_4$</TEX>) gas in a conventional low-pressure chemical vapor deposition vertical furnace. If the p-type polysilicon is formed by boron implantation into undoped polysilicon, the plasma nitridation (PN) process is added on the oxide in order to suppress boron penetration that can be caused during the thermal treatments used in fabrication. In-situ boron doped polysilicon deposition can complete p-type polysilicon film with only one deposition process and need not the PN process, because there is not interdiffusion of dopant at the intermediate temperatures of the subsequent steps. Since in-situ boron doped polysilicon films have higher work function than that of n-type polysilicon and they are compatible with the underlying oxide, they may be promising materials for improving memory cell characteristics if we make its profit of these physical properties.

Improvement in Mobility and Negative-Bias Temperature Instability in Metal–Oxide–Semiconductor Field-Effect Transistors with Atomic-Layer-Deposited Si–Nitride/SiO2 Stack Dielectrics

Carrier mobility and negative-bias temperature instability (NBTI) characteristics were studied for p+ polycrystalline Si-gated metal–oxide–semiconductor field-effect transistors (MOSFETs) with various gate dielectrics: atomic-layer-deposited (ALD) Si–nitride/SiO2 stack, plasma-nitrided SiON, and pure-SiO2 dielectrics. MOSFETs with the ALD Si–nitride/SiO2 stack dielectrics offer the lowest interface trap density and highest carrier mobility among the three samples owing to their superior ability to suppress boron penetration. P-channel MOSFETs with the ALD stack dielectrics exhibit an abnormal NBTI behavior: threshold voltage shift (ΔVth) is positive at the early stress stage and then becomes negative at longer stress times. Such a turnaround behavior may be attributed to the presence of preexisting neutral electron traps in the Si–nitride/SiO2 stack dielectrics, which may lead to the net ΔVth of the stack dielectrics stressed at a low voltage to be even smaller than that of the pure-SiO2 dielectrics. The above-mentioned findings suggest that the ALD Si–nitride/SiO2 stack dielectrics are very promising for sub-0.1-µm MOSFETs.

Atomic Layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics for future high-speed DRAM with enhanced reliability

Atomic layer-deposited (ALD) Si-nitride/SiO/sub 2/ stack gate dielectrics were applied to high-performance transistors for future scaled DRAMs. The stack gate dielectrics of the peripheral pMOS transistors excellently suppress boron penetration. ALD stack gate dielectrics exhibit only slightly worse negative-bias temperature instability (NBTI) characteristics than pure gate oxide. Enhanced reliability in NBTI was achieved compared with that of plasma-nitrided gate SiO/sub 2/. Memory-cell (MC) nMOS transistors with ALD stack gate dielectrics show slightly smaller junction leakage than those with plasma-nitrided gate SiO/sub 2/ in a high-drain-voltage region, and have identical junction leakage characteristics to transistors with pure gate oxide. MCs having transistors with ALD stack gate dielectrics and those with pure gate oxide have the identical retention-time distribution. Taking the identical hole mobility for the transistors with ALD stack gate dielectrics to that for the transistors with pure gate oxide both before and after hot carrier injection (previously reported) into account, the ALD stack dielectrics are a promising candidate for the gate dielectrics of future high-speed, reliable DRAMs.

Suppression of Gate Depletion in p+-Polysilicon-Gated Sub-40 nm pMOSFETs by Laser Thermal Processing

Laser thermal processing (LTP) was investigated as a gate pre-annealing technique and its advantages over rapid thermal annealing (RTA) with regard to both gate activation and suppression of boron penetration were confirmed by evaluating the electrical characteristics of sub-40 nm p-metal oxide semiconductor field effect transistors (pMOSFETs). Laser annealing transformed amorphous Si in which high doses of boron were implanted into poly-Si with highly activated boron profiles down to the gate/gate oxide interface. By suppressing gate depletion with suppressing boron penetration, LTP results in an on-current at Ioff=70 [nA/µm] that is 4% greater than that in a device fabricated using conventional RTA. The off-state Ig current that flows mainly from the p+ poly-Si gate to the drain overlap region is smaller in devices fabricated using LTP because the reduced roughness of the poly-Si gate/gate oxide interface in these devices reduces the local electric field enhancement.

Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond

Boron penetration from the poly-silicon gate to the silicon substrate through gate dielectrics is a crucial problem in the dual gate complementary metal-oxide semiconductor (CMOS) process. Therefore, the plasma nitridation technique has been studied well, and it has succeeded to suppress boron penetration. However, boron penetration occurs not only from the doped poly-silicon gate but also from the substrate, and resulting in several degradations of gate-oxide characteristics. On the other hand, the boron concentration of source/drain (S/D) extension has been increasing with gate shrinkage. We found that boron penetration from the S/D extension becomes a crucial problem in gate leakage and gate-oxide integrity, particularly for nanoscale positive-channel MOS (pMOS). In this study, we examined several treatments in detail to suppress boron penetration from the S/D extension, and demonstrated that the plasma nitridation treatment after gate etching is the best solution for 65-nm node CMOS and beyond.

Suppression of Boron Penetration in P+-Poly-SiGe Gate P-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Using NH3-Nitrided and N2O-Grown Gate Oxides

High-performance p+-poly-SiGe-gate p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) have been fabricated using NH3-nitrided or N2O-grown oxide instead of the conventional O2-grown oxide. It is found that NH3-nitrided or N2O-grown oxide can suppress boron penetration in the p+-poly-SiGe gate, which improves the integrity of gate dielectrics, resulting in a low flat-band voltage shift, subthreshold swing, and drain-induced barrier lowering.

Electrical characteristics and suppressed boron penetration behavior of thermally stable HfTaO gate dielectrics with polycrystalline-silicon gate

The thermal stability and electrical characteristics of HfTaO gate dielectric with polycrystalline-silicon gate have been investigated. The incorporation of Ta into HfO2 enhances the crystallization temperature of film dramatically. Transmission electron microscopy micrographs confirm that HfTaO with 43% Ta film remains amorphous even after activation annealing at 950°C for 30s, and the formation of low-κ interfacial layer is observably reduced. The capacitance–voltage curve of metal–oxide–semiconductor capacitor using HfTaO gate dielectric fits well with simulated curve, indicating good interface property between HfTaO and substrate. In addition, the boron penetration behaviors of HfTaO films are sufficiently suppressed as manifested by the narrow flat-band voltage shift. The negligible flat-band voltage shift in HfTaO with 43% Ta film is observed and attributed to its amorphous structure after device fabrication.

Roles of nitrogen incorporation in HfAlOx(N) gate dielectrics for suppression of boron penetration

We have investigated impacts of nitrogen incorporation into HfAlOx films on the gate leakage currents and the flat band voltage VFB shifts. Also, a role of O–Hf–N bonding states in HfAlOx(N) in suppression of boron penetration is discussed. The nitrogen concentration CN in HfAlOx(N) was controlled by changing the NH3 annealing temperature at the step of the layer-by-layer deposition and annealing process as well as the O2 annealing temperature of post-deposition annealing. The CN over 10 at. % in HfAlOx(N) films effectively suppressed boron penetration as revealed by very slow diffusion in Hf3N4 films and the formation of boron-nitrogen remote complex in HfOx(N), preserved the amorphous structure and reduced the VFB shift compared to the case of HfAlOx without nitrogen incorporation, while CN exceeding 13 at. % led to a significant increase of the gate leakage current. This suggests the excess O–Hf–N bond formation enhanced the leakage current.

Effects of Process and Gate Doping Species on Negative- Bias-Temperature Instability of p-Channel MOSFETs

The effects of poly-Si gate doping type and species as well as thermal treatments on negative-bias-temperature instability (NBTI) of p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) were investigated. We found that devices with -poly-Si gate depict a smaller threshold voltage shift after bias-temperature stressing, compared to their -poly-Si-gated counterparts. By carefully controlling the thermal budget to suppress boron penetration, NBTI can be reduced by fluorine incorporation in -poly-Si-gated devices. Finally, NBTI is found to be aggravated in devices subjected to postmetal-annealing, highlighting the important role of hydrogen bonds. © 2004 The Electrochemical Society. All rights reserved.

Boron-Retarded Gate Dielectric Formed by Dry Oxidation of Thermal Nitride

We have proposed an approach to grow thin oxynitride gate dielectric (equivalent oxide with the capability for preventing boron penetration. In this method, oxynitride is formed by dry oxidation of ultrathin thermal nitride grown in low pressure. The secondary ion mass spectroscopy profile indicates that its nitrogen peak is located at the gate dielectric surface and possesses concentrations as high as Transmission electron spectroscopy analysis shows that this oxynitride has uniform thickness and a very smooth interface with the Si substrate. Surface roughness is also evaluated by atomic force spectroscopy and exhibits acceptable roughness for device operation. The capability to suppress boron penetration is further proven by the flatband voltage shift in C-V measurement. In addition, its practicality for device operation is also characterized by electrical performances for gate dielectric integrity and reliability. Most importantly, this process is not complicated and fully compatible with existent ultralarge scale integration technology. © 2003 The Electrochemical Society. All rights reserved.

Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics

P/sup +/-poly-Si gate MOS transistors with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics (EOT=2.50 nm) have been fabricated. Similar to the reference samples with SiO/sub 2/ gate dielectrics (T/sub ox/=2.45 nm), clear saturation characteristics of drain current are obtained for the samples with stack gate dielectrics. Identical hole-effective mobility is obtained for the samples with the SiO/sub 2/ and the stack gate dielectrics. The maximum value of hole-effective mobility is the same (54 cm/sup 2//Vs) both for the stack and the SiO/sub 2/ samples. Hot carrier-induced mobility degradation in transistors with the stack gate dielectrics was found to be identical to that in transistors with the SiO/sub 2/ gate dielectrics. In addition to the suppression of boron penetration, better TDDB characteristics, and soft breakdown free phenomena for the stack dielectrics (reported previously), the almost equal effective mobility (with respect to that of SiO/sub 2/ dielectrics) has ensured the proposed stack gate dielectrics to be very promising for sub-100-nm technology generations.

A study of nitrogen peak location in gate oxides grown on nitrogen implanted substrates and its impact on boron penetration

This work investigates properties of gate oxides grown on nitrogen-implanted substrates. It was demonstrated that the location of nitrogen peak in the gate oxide, once fixed at the beginning of the oxidation step, does not change with continued oxidation. Using this property, nitrogen peak was engineered near the gate oxide interface with substrate and was shown to suppress boron penetration more effectively without any significant degradation of the channel mobility in comparison to the case where the nitrogen peak is located within the bulk of the gate oxide.

Highly Reliable Dynamic Random Access Memory Technology for Application Specific Memory with Dual Nitrogen Concentration Gate Oxynitrides Using Selective Nitrogen Implantation

A polymetal dual gate dynamic random access memory (DRAM) for application specific memory (ASM) with dual nitrogen concentrated oxynitrides was developed for the first time. This technology uses selective nitrogen implantation performed just after gate oxidation. The nitrogen concentration of p-type metal oxide semiconductor (PMOS) in gate dielectric combined with nitrogen implantation and NO (nitric oxide) annealing is sufficiently high to suppress boron penetration, whereas that of the cell array transistor (cell-Tr) and n-type metal oxide semiconductor (NMOS) is sufficiently low to maintain the threshold voltage (Vth) without increasing the channel dosage by using only NO annealing.

Effect of nitridation on the reliability of thick gate oxides

In this work the effect of nitridation on the reliability of thick (60 nm) gate oxides used in discrete power MOSFETs is investigated. Nitridation was carried out by post-oxidation anneal in N 2O at 1000 °C. Secondary ion mass spectroscopy characterization did show that the nitrogen resulting from N 2O nitridation piles up in the oxide at the Si–SiO 2 interface regardless of nitridation time. The results obtained show improved breakdown field ( E bd), and charge-to-breakdown ( Q bd) characteristics for nitrided thick oxides. Also, lower mid-bandgap interface trap density ( D it) was observed in the case of nitrided oxides. Key conclusion from this experiment is that nitridation of thick (>50 nm) gate oxide performed to suppress boron penetration into the MOSFET channel region is not having an adverse effect on its electrical characteristics.

Suppressed boron penetration in p+ polycrystalline-Si/Al2O3/Si metal–oxide–semiconductor structures

We demonstrate a suppressed boron penetration in p+ polycrystalline-Si (poly-Si)/Al2O3/n-Si metal–oxide–semiconductor (MOS) capacitors using a remote plasma nitridation (RPN) of Al2O3 surface. The B penetration was sufficiently suppressed for temperature to 850 °C in N2 for 30 min as manifested by the negligible flat band shift (ΔVFB) and insignificant B diffusion. The nitrogen (N) incorporation in Al2O3 surface appears to effectively impede the B diffusion into the Si channel. Increased gate leakage current for the n+ poly-Si/RPN-Al2O3/p-Si n-type MOS capacitors was observed and attributed to the reduced band gap energy of RPN-Al2O3 due to the formation of AlN and bulk defects due to RPN. Optimization of N concentration is required for the suppressed B penetration and leakage reduction.

Degradation and SILC Effects of RPECVD sub-2.0nm Oxide/Nitride and Oxynitride Dielectrics Under Constant Current Stress

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.

Suppression of boron penetration through thin gate oxides by nitrogen implantation into the gate electrode

PMOS devices with different amounts of nitrogen incorporated into the gate electrode by implantation were manufactured. Nitrogen implantation into the gate electrode of PMOS devices was applied before BF2 implantation and annealing by rapid thermal annealing for doping the gate electrode. The thickness of the gate oxides grown at low pressure in dry oxygen by rapid thermal oxidation were 4.1 down to 2.8 nm. The influence of the nitrogen implant on the penetration of boron ions through the ultra-thin gate oxides into the channel region was investigated by electrical and SIMS measurements. Boron was effectively prevented from diffusion by high nitrogen concentrations at the polysilicon/gate oxide interface without degrading the reliability. In return, increased sheet resistivities and gate depletion have to be taken into account when high nitrogen concentrations are incorporated within the polysilicon gate electrode.

Suppression of boron penetration through thin gate oxides by nitrogen implantation into the gate electrode in PMOS devices

PMOS devices with and without nitrogen implant into the gate electrode before doping with boron and with nitridation of the gate oxide were manufactured. The influence of nitrogen on the penetration of boron ions into the substrate through ultra-thin gate oxides was investigated by electrical and SIMS measurements. Boron diffusion can be effectively prevented by high nitrogen concentrations located immediately above the gate oxide and within the polysilicon gate electrode.