Suppression Of Short-channel Effects Research Articles

(Invited) Technology Scaling from Bulk to Fin and Nano-Sheet Transistors

In recent years, scaling of semiconductor device has progressed, leading to the development of advanced semiconductor devices with code names of below 10-nm. Various new materials and technologies have been introduced to accompany the miniaturization of semiconductor devices. First, the resistivity of aluminum became higher due to miniaturization, and aluminum was replaced by copper as the wiring metal. Then, to increase the gate capacitance of MOS field-effect transistors, the thickness of the gate insulating film (SiO2) was reduced to the limit, and as a result, gate leakage current could no longer be suppressed, which led to the introduction of a high-k gate insulating films (HfO2).The next bottleneck in miniaturization was the suppression of short channel effects. As the gate length became smaller, the gate electrode's control over the channel decreased, resulting in the generation of a small amount of leakage current even when the transistor is turned off, and the threshold voltage also fluctuated as the gate length became shorter, which interfered with circuit operation. To suppress the short-channel effect, the conventional bulk transistor was replaced around 2011 by a transistor with an upright channel, called a fin transistor. The purpose of this is to increase the gate's dominance over the channel, suppress leakage current, and prevent the short-channel effect by having multiple opposing gate electrodes for the raised channel. However, since the channel width of a fin transistor corresponds to the sidewall height, a fin with a high height must be formed to increase the channel width and gain total current density, which has been a problem in terms of processing technology. In addition, in order to increase the current, a layout configuration with multiple fins formed horizontally had to be adopted, which increased the area of the chip, thereby hindering the integration of the chip.This leads to an increase in the area of the chip, which in turn hinders high integration of the chip. The nanosheet transistor is a new transistor structure in which multiple 10-nm-thick "nanosheets" of silicon are stacked in the height direction to form the transistor channel. Another major feature of this nanosheet transistor is the use of a gate all-around structure, which is a further development of the gate structure of the double gate type. As a result, this structure is the most effective in suppressing short channels. Furthermore, by stacking nanosheets vertically, it is possible to increase the current density per unit area without increasing the chip area. As a further evolution of the nanosheet transistor, a complementary FET (CFET) structure is currently being considered, in which pMOS and nMOS are stacked vertically to realize a CMOS circuit in the vertical direction. So far, CFETs with pn stacked in silicon and attempts to form CFETs by laminating silicon and germanium together have been presented. In Japan, research and mass production of this nanosheet type transistor has recently been planned, overtaking mass production of fin transistors.

Progress in the suppression of short-channel effects: Materials and structure

With the rapid development of integrated circuit (IC) technology, the size of devices has been continuously shrinking. While this trend has led to increased integration density, improved device reliability, and reduced costs, it has also resulted in performance degradation of metal-oxide-semiconductor field-effect transistors (MOSFETs) due to the short channel effect (SCE). This paper provides a comprehensive review of the most recent techniques that can mitigate the short channel effect in MOSFETs, with a focus on semiconductor materials and device structures. These techniques include decades-long advancements in doping and high- dielectric materials, as well as emerging structures such as Fin field-effect transistors (FinFETs), Gate-all-around field-effect transistors (GAAFETs), Forksheet field-effect transistors, and complementary field-effect transistors (CFETs). This paper can greatly assist researchers in establishing a theoretical foundation, identifying research problems and voids, and identifying hot spots and trends in short channel effect research through a comprehensive analysis of the existing research literature.

Device Optimization for Short-channel Effects Suppression in UFETs

Device Optimization for Short-channel Effects Suppression in UFETs

Suppression of Short Channel Effects for a SiC MOSFET Based on the S-MOS Cell Concept

This paper investigates the short channel effects (SCE) of the recently proposed Singular Point Source MOS (S-MOS) SiC MOSFET. The study was carried out using 2D and 3D TCAD simulations for a planar, trench and S-MOS 1200V SiC MOSFETs for the IV output characteristics up to 1200V and under short circuit transient conditions. The S-MOS device shows no SCE up to the rated voltage when compared to reference planar and trench devices which exhibit strong SCE. This is due to the appropriate P++ protection of the N++ source and the electric field shielding due to the narrow mesa dimensions between orthogonal trenches where the channel is located.

Suppress Short Channel Effects on Split Channel-Cylindrical GAA TFET Using Buried Oxide Layer

The idea of a buried oxide layer (BOx) in a split channel Gate All Around-Tunnel Field Effect Transistor (GAA-TFET) was investigated in this paper. This work examined the impact of buried oxide layer on the device's performance. With the BOx layer present and channel length of 20nm, the channel area of the TFET device investigated in this study is divided equally on the same side. The doping concentration has been transferred to the split channel on the drain side. The device’s performance was examined using numerical simulation utilizing simulation software of CAD devices. The final results which incorporate the buried oxide layer were being compared to the uniform split channel GAA-TFET. The parameters like ON current (Ion),OFF current (Ioff), subthreshold swing (SS) and electric-field (E) intensity are observed and compared with silicon (Si) based GAA-TFET and Indium phosphide (InP) based GAA-TFET. It is found that InP based GAA-TFET with buried oxide layer is more advanced device design than the others with Ion and Ioff of 3.02 x 10-05 A/um and 2.09 x 10-22 A/um, respectively.

Device modeling of two-steps oxygen anneal-based submicron InGaZnO back-end-of-line field-effect transistor enabling short-channel effects suppression

Amorphous oxide semiconductor (AOS) field-effect transistors (FETs) have been integrated with complementary metal-oxide-semiconductor (CMOS) circuitry in the back end of line (BEOL) CMOS process; they are promising devices creating new and various functionalities. Therefore, it is urgent to understand the physics determining their scalability and establish a physics-based model for a robust device design of AOS BEOL FETs. However, the advantage emphasized to date has been mainly an ultralow leakage current of these devices. A device modeling that comprehensively optimizes the threshold voltage (VT), the short-channel effect (SCE), the subthreshold swing (SS), and the field-effect mobility (µFE) of short-channel AOS FETs has been rarely reported. In this study, the device modeling of two-steps oxygen anneal-based submicron indium-gallium-zinc-oxide (IGZO) BEOL FET enabling short-channel effects suppression is proposed and experimentally demonstrated. Both the process parameters determining the SCE and the device physics related to the SCE are elucidated through our modeling and a technology computer-aided design (TCAD) simulation. In addition, the procedure of extracting the model parameters is concretely supplied. Noticeably, the proposed device model and simulation framework reproduce all of the measured current–voltage (I–V), VT roll-off, and drain-induced barrier lowering (DIBL) characteristics according to the changes in the oxygen (O) partial pressure during the deposition of IGZO film, device structure, and channel length. Moreover, the results of an analysis based on the proposed model and the extracted parameters indicate that the SCE of submicron AOS FETs is effectively suppressed when the locally high oxygen-concentration region is used. Applying the two-step oxygen annealing to the double-gate (DG) FET can form this region, the beneficial effect of which is also proven through experimental results; the immunity to SCE is improved as the O-content controlled according to the partial O pressure during oxygen annealing increases. Furthermore, it is found that the essential factors in the device optimization are the subgap density of states (DOS), the oxygen content-dependent diffusion length of either the oxygen vacancy (VO) or O, and the separation between the top-gate edge and the source-drain contact hole. Our modeling and simulation results make it feasible to comprehensively optimize the device characteristic parameters, such as VT, SCE, SS, and µFE, of the submicron AOS BEOL FETs by independently controlling the lateral profile of the concentrations of VO and O in two-step oxygen anneal process.

Computational Analysis of Joule Heating Effect in Triple Material Gate AlGaN/GaN High Electron Mobility Transistor

Aluminum gallium nitride (AlGaN)/gallium nitride (GaN) high electron mobility transistor (HEMT) has shown great potential and superiority over other devices in high power and high speed-based systems [1-4]. Recently, a novel AlGaN/GaN HEMT structure named triple material gate (TMG) HEMT has been proposed in [5] in which the gate contact is composed of three metals with different work functions. TMG HEMT ensures high carrier velocity and better suppression of short channel effects. In this work, a two-dimensional electro-thermal model has been developed to investigate the joule heating effect in TMG AlGaN/GaN HEMT using the software COMSOL [6]. The current continuity and heat transport equations are solved self-consistently to obtain the temperature distribution profile in various layers of the device. Thermal efficiency of TMG HEMT is compared with dual material gate and single material gate HEMT. It has been found that, besides providing better current carrying capability, TMG HEMT shows optimum thermal performance. Moreover, the variation of peak temperature in the channel with drain and gate voltages is analyzed to study the bias voltage dependence of the device temperature rise. Effects of several device parameters like total channel length, spontaneous and piezoelectric polarization induced charges and ratio of lengths of control and screen gates, on the thermal performance have also been explored. Simulations are carried out for the device lying on different substrate materials (Sapphire, GaN, Si and SiC) with varying thermal conductivity to demonstrate their performance in heat removal capacity. This simulation model can serve as a very useful tool to comprehend the thermal behavior of the device for high power and high frequency applications.

Synthesis of Low-Voltage Logic Gates on Surrounding Gate SOI CMOS Nanotransistors

We discuss the issues of synthesis of low-voltage logic gates on cylindrical surrounding gate SOI CMOS nanotransistors in the supply voltage range up to 0.8 V. In this transistor architecture, it becomes possible to more effectively control the charge in its working area, primarily due to its design parameters. It is also characterized by effective suppression of short-channel effects and a low capacitance value. This leads to a decrease in the level of power dissipation in combination with a reduction in the occupied area. TCAD models of n- and p-types nanotransistors have been developed. The anomalous behavior of the dependence of the threshold voltage on the diameter of the working area is revealed, which is associated with the peculiarities of the manifestation of short-channel effects due to the capacitive interaction of the gate-channel regions and drain-source transitions at small gate lengths. They were used to select prototypes of transistors with optimal parameters for the synthesis of complex logic gates with low supply voltage. Using the mathematical core of the HSPICE program, the dynamic characteristics of the developed physical models of the inverter, the inverter chain, and the XOR2 are numerically investigated. At control voltages of 0.8 V and a frequency of 50 GHz, the inverter model predicts a maximum switching delay of 3.3 ps, a limit level of active power of 1.1 mkW, static 0.3 pW, the XOR2 predicts a maximum switching delay of 8.6 ps, a limit level of active power of 4.9 mkW, static 1.5 pW. The minimum of the product "delay * power" of the adder is at a supply voltage of 0.72 V. Its position does not depend on the set of input signals. At the same time, the maximum switching delay is 10.8 ps, the maximum active power level is 3.9 mkW. The totality of the obtained characteristics allows us to consider the analyzed transistor architecture for creating low-power electronic devices.

GaN FinFETs and trigate devices for power and RF applications: review and perspective

Gallium nitride (GaN) is becoming a mainstream semiconductor for power and radio-frequency (RF) applications. While commercial GaN devices are increasingly being adopted in data centers, electric vehicles, consumer electronics, telecom and defense applications, their performance is still far from the intrinsic GaN limit. In the last few years, the fin field-effect transistor (FinFET) and trigate architectures have been leveraged to develop a new generation of GaN power and RF devices, which have continuously advanced the state-of-the-art in the area of microwave and power electronics. Very different from Si digital FinFET devices, GaN FinFETs have allowed for numerous structural innovations based on engineering the two-dimensional-electron gas or p–n junctions, in both lateral and vertical architectures. The superior gate controllability in these fin-based GaN devices has not only allowed higher current on/off ratio, steeper threshold swing, and suppression of short-channel effects, but also enhancement-mode operation, on-resistance reduction, current collapse alleviation, linearity improvement, higher operating frequency, and enhanced thermal management. Several GaN FinFET and trigate device technologies are close to commercialization. This review paper presents a global overview of the reported GaN FinFET and trigate device technologies for RF and power applications, as well as provides in-depth analyses correlating device design parameters to device performance space. The paper concludes with a summary of current challenges and exciting research opportunities in this very dynamic research field.

Suppression of short channel effects in ferroelectric Si junctionless transistors with a sub-10 nm gate length defined by helium ion beam lithography

Short channel effects in Si junctionless transistors with a gate length below 10 nm are reduced by the ferroelectric Hf0.5Zr0.5O2gate oxide.

Silicon Nanowire Parameter Extraction Using DFT and Comparative Performance Analysis of SiNWFET and CNTFET Devices

The performance and scalability of silicon nanowire field-effect transistor (SiNWFET) and carbon nanotube field-effect transistor (CNTFET) with surround gate geometry were studied using such tools as material exploration and design analysis (MedeA) and device modeling and simulation SilvacoTCAD. The SiNWFET and CNTFET with gate-all-around (GAA) structure offer good gate electrostatic control, high On-current and better suppression of short-channel effects with complete encirclement of the device channel. Rather than using the bulk properties of silicon, estimation of properties silicon nanowire (SiNW) was made using MedeA VASP tool based on density functional theory (DFT). In this study, the device input (ID–VGS) and output (ID–VDS) have been analyzed and parameters like threshold voltage, IOn/IOff ratio, drain induced barrier lowering and sub-threshold slope extracted, and comparison is made between SiNWFET and CNTFET devices. The results point towards the DFT-based material parameter estimation to incorporate the quantum effects and use of SiNW/CNT-based GAA structure below 10 nm to meet scaling targets. The results suggest that the SiNWFET and CNTFET device with GAA geometry could be a better alternative to conventional MOSFETs and FinFET for numerous high-performance and low-power device applications.

Simulation of the Nanoscale Joint Surrounding Gate SOI MOSFET Characteristics

In order to solve the current problem of increasing the efficiency of modern electronic circuits, the applicability of a nanoscale joint surrounding gate MOSFET with oval work area is discussed. The design and principle of its operation are considered. This concept involves of jointing the working areas of n-channel and p-channel MOSFETs. In fact, the JSMOSFET consists of two "glued" along the halves of MOSFETs: one - nchannel and the other - p-channel, but with one common gate. We analyze the applicability of the design of an oval-shaped protected area. In our case, the contact of two heterogeneously doped regions occurs in the plane passing through the small axis of the oval. The main channels are formed in zones associated with the large axis of the oval. This achieves the main goalincreasing the number of charge carriers. At the same time, the efficiency of short-channel effect suppression is maintained and a high current level of the transistor is provided in the strong inversion mode. By the developed TCAD model of a nanoscale joint surrounding gate MOSFET with an oval work area the electrophysical characteristics of several prototypes with different transverse dimensions were numerically calculated at a supply voltage of 0.5 V. From the simulation results, it follows that all prototypes are low-voltage devices that can function at voltages below 0.5 V in the gigahertz frequency range with a high gain. The proposed devices perform the function of inverting the input signal without distortion. From the comparison of modeling data, the scope scaling capabilities are determined. The obtained results create prerequisites for the development of the proposed transistor architecture, since electronic chips created on their basis will differ in low power supply voltage, high performance, and minimal occupied area, which meets modern requirements for transistors for analog and digital applications.

Analysis of Temperature Effect in Quadruple Gate Nano-scale FinFET

Quadruple gate FinFET is a promising candidate among other multi-gate MOS devices due to it’s better scalability and higher short channel effect suppression capability in advanced technology node. In this work, we report the effect of temperature on various performance metrics of quadruple gate FinFET like electrostatic integrity, carrier mobility, switching ratio, analog/RF, and linearity parameters with the help of well-calibrated numerical device simulation-based study (TCAD). While increasing the temperature from 250 °K to 450 °K, due to the enhanced bulk phonon scattering, degradation in carrier effective mobility is observed. Sub-threshold swing and drain induced barrier lowering coefficient vary linearly with temperature. At high temperature, due to the reduced carrier mobility, degradation in the analog figure of merits is observed. RF performance parameters also degrade primarily due to the enhanced gate capacitance and reduced trans-conductance. However, some linearity parameter improves at high temperature due to the reduced magnitude of the higher-order derivative of trans-conductance. Another major contribution of this work is, we demonstrate the inflection point or temperature compensation point in some analog/RF performance metrics where the device characteristics almost invariant with temperature.

Suppression of short-channel effects in normally-off GaN MOSFETs with deep recessed-gate structures

We have demonstrated the suppression of short-channel effects (SCEs) in normally-off GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with deep recessed-gate structures. TCAD simulation results show that the electric field concentration is effectively reduced at the recessed edge of MOSFETs with deeper recessed-gate structures. To demonstrate suppression of SCEs, MOSFET gate structures with recess depths ranging from 45 to 165 nm were fabricated and evaluated. Experimental results show that deeper recessed-gate structures are highly effective for suppressing drain-induced barrier lowering and improving subthreshold swing and threshold voltage roll-off.

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High ION/IOFF Ratio

We successfully fabricate the Si0.8Ge0.2 channel fin field-effect-transistor (FinFET) with 5 nm ultra-thin fin width and high aspect ratio ( $\sim 10\times $ ) on silicon-on-insulator (SOI) substrate by simple two-step dry etching. In comparison of the conventional Si FinFET, our proposed SiGe ultra-thin FinFETs (Si0.8Ge0.2 UT-FinFET) at VD = 0.75 V & VG = 1.5 V shows higher ON-state current (1 mA/fin), even achieve lower OFF-state current (0.2 nA/fin) and steep subthreshold slope (SS) of 76 mV/decade, which is owing to the better gate control given by the ultra-thin fin channel. In addition, this work also exhibits the suppression of short channel effect (SCE) with very small drain induced barrier-lowering (DIBL) of 4 mV/V.

Advanced Short-Channel-Effect Modeling With Applicability to Device Optimization—Potentials and Scaling

Silicon-thickness scaling has been used as the main parameter for short-channel-effect (SCE) reduction. Nevertheless, SCEs are still present in advanced thin-layer MOSFETs. Here, for enlarging the insight into SCE suppression, a new compact model is developed based on the SCE origin, which is demonstrated to be the potential distribution at the contact/channel junctions. In addition, it is shown that the potential distribution along the MOSFET channel can be modeled by overlapping potentials coming from the source and drain sides. The developed compact model is verified with leading-edge multi-gate MOSFETs, further demonstrating that device optimization with SCE suppression becomes possible due to the accurate reproduction of the device characteristics. The model validation is done with 2-D device simulations for different channel lengths, oxide, and silicon thicknesses as well as channel-doping concentration, for which an accurate compact-model reproduction is achieved. In addition, the general properties of the potential-based SCE model are extended to other MOSFET device structures.

Suppression of Short-Channel Effects in 4H-SiC Trench MOSFETs

Submicron 4H-SiC MOSFETs are attractive for high frequency operation of 4H-SiC integrated circuits. However, the short channel effects, such as threshold voltage lowering, would be induced at the short-channel devices. In this work, short channel effects were investigated with planar and trench 4H-SiC MOSFETs, and the suppression of the short channel effect with the trench structure was achieved.

Sub-10 nm Monolayer MoS2 Transistors Using Single-Walled Carbon Nanotubes as an Evaporating Mask.

Transition-metal dichalcogenides are promising challengers to conventional semiconductors owing to their remarkable electrical performance and suppression of short-channel effects (SCEs). In particular, monolayer molybdenum disulfide has exhibited superior suppression of SCEs owing to its atomic thickness, high effective carrier mass, and low dielectric constant. However, difficulties still remain in large-scale stable fabrication of nanometer-scale channels. Herein, a method to fabricate electrodes with sub-10 nm gaps was demonstrated using horizontally aligned single-walled carbon nanotubes as an evaporation mask. The widths of the nanogaps exhibit robust stability to various process parameters according to the statistical results. Based on these nanogaps, ultrashort-channel length monolayer MoS2 field-effect transistors were produced. Monolayer MoS2 devices with a 7.5 nm channel length and a 10 nm thick HfO2 dielectric layer exhibited excellent performances with an ON/OFF ratio up to 107, a mobility of 17.4 cm2/V·s, a subthreshold swing of about 120 mV/dec, and a drain-induced barrier lowering of about 140 mV/V, all of which suggest a superior suppression of SCEs. This work provides a universal and stable method for large-scale fabrication of ultrashort-channel 2D-material transistors.

Subthreshold modeling of nanoscale germanium-tin (GeSn)-on-insulator MOSFETs including quantum effects

Although germanium-tin (GeSn) channel p-MOSFETs exhibit outstanding performance compared to other p-MOS transistors, their accurate analytical model has not yet been reported. In this paper, we present, for the first time, a 2-D surface-potential-based sub-threshold model for GeSn-on-insulator (GeSnOI) MOSFETs taking into account the interface-trapped and fixed-oxide charge densities, and also quantum effects. Unlike most of the earlier models applied to elementary and undoped semiconductor channels, the present model embraces variations in the alloy composition as well as doping concentration in the channel. Furthermore the model neither supports iterations nor involves any fitting parameters throughout the derivation, and hence it is physical, predictive, and applicable to circuit simulators like SPICE. We calculate various device parameters such as threshold voltage Vth, threshold voltage roll-up, drain induced barrier lowering DIBL and subthreshold slope SS related to short channel effects (SCEs) of GeSnOI p-MOSFETs for Sn contents ranging 0–6% and channel thickness from 5 to 10 nm. The obtained results show that the GeSnOI MOSFET with channel thickness of 5 nm yields the lowest value of Vth, DIBL, SS and Vth-shift indicating suppression of SCEs. Our model is verified by comparing analytical results for various device parameters with corresponding numerical simulation results and also with limited experimental data available in the literature.

Leading-Edge Thin-Layer MOSFET Potential Modeling Toward Short-Channel Effect Suppression and Device Optimization

A novel compact model has been developed, which considers the origin of the short-channel effect (SCE) on the basis of the potential distribution along the channel. Thus an enlargement of the insight into SCE suppression in advanced thin-layer MOSFETs is enabled. The model is extended to include the diffusion region resistance effects caused by the drain-side doping by applying the methodology of the industry-standard high-voltage MOSFET model HiSIM_HV. Usage for studying possible device optimizations revealed that clear improvements in the subthreshold characteristics due to suppression of SCEs can be achieved by slightly increasing the drain-side diffusion resistance. Disadvantageous effects on the device and circuit performances were found to be negligible.