Supply Voltage Research Articles

Design of energy-efficient full subtractor circuit at near threshold computing for signal processing application

Abstract Energy Efficiency is a critical factor while designing integrated circuits. Therefore, a 1-bit full subtractor (FS) cell is proposed for lower power application by employing Gate Level Body Biasing (GLBB) scheme for Near Threshold Computing (NTC) application to conquer a unique module for achieving full swing borrow output.We evaluate power, delay, energy and the product of energy with delay (EDP) metrics with respect to C-CMOS full subtractor. The proposed feedback based with FS with GLBB technique has a total die area of 60.02 μm2, while the average power, delay, and energy are 1138 pW, 242 ns, and 27.53 aJ, respectively. The results revealed that our proposed subthreshold hybrid FS circuit with GLBB scheme successfully achieved more than 10.46% average power consumption, 26.58% energy consumption reductions, and 17.98% EDP savings compared to conventional CMOS configuration and other hybrid counterparts. GLBB circuits with FS achieve performance levels that are not affordable in C-CMOS, DTMOS,and GLBB with full adder configurations. Therefore, the FS circuit serves as an efficient divider circuit in terms of detecting objects for image processing applications.

Realizing In-Memory Computing using Reliable Differential 8T SRAM for Improved Latency

Traditional von Neumann computing architectures suffer from high energy and lower speed as compared to the requirements of modern applications like those required in neural network accelerators. A modified differential eight transistor (8 + T) static random access memory (SRAM)-based in-memory computing (IMC) structure was presented for realizing bit-wise Boolean logic operations. The 8 + T SRAM-IMC is designed at the 32 nm technology node with throughput of 2.1849, 2.4815, 2.5795, 2.6240, 2.6495, 2.6619, 2.6690, 2.6732, and 2.6749 giga outputs per second for 0.5 to 1.3 V supply voltage range, respectively. The differential 8T cell used to implement logic operations supports NAND and NOR operations with minimal overhead while also performing the standard storage operation with added stability over the conventional 6T and 8T SRAM cells. The SRAM-IMC offers reliable Boolean logic operations by using asymmetric sensing strategy for all process corners, TT, SS, SF, FS, and FF for an operating temperature range of 220 K to 400 K. Monte Carlo simulation considering global threshold voltage deviation of 50 mV was performed for various operating conditions to study the impact of variations on design parameters such as latency.

A High-Efficiency Piezoelectric Energy Harvesting and Management Circuit Based on Full-Bridge Rectification

This paper presents a high-efficiency piezoelectric energy harvesting and management circuit utilizing a full-bridge rectifier (FBR) designed for powering wireless sensor nodes. The circuit comprises a rectifier bridge, a fully CMOS-based reference source, and an energy management system. The rectifier bridge uses a PMOS cross-coupled structure to greatly reduce the conduction voltage drop. The CMOS reference source provides the necessary reference voltage and current. The energy management system delivers a stable 1.8 V to the load and controls its operation in intermittent bursts. Fabricated with a 110 nm CMOS process, the circuit occupies an area of 0.6 mm2, and is housed in a QFN32 package. Test results indicate that under 40 Hz frequency and 4 g acceleration vibrations, the chip’s energy extraction power reaches 234 μW, with the load operating every 3 s at a supply voltage of 1.8 V. Thus, this FBR interface circuit efficiently harnesses the energy output from the piezoelectric energy harvester.

Radiation Hardened Read-Stability and Speed Enhanced SRAM for Space Applications

With the advancement of CMOS technology, the susceptibility of SRAM to single node upset (SNU), double node upset (DNU), and multiple node upset (MNU) induced by radiation has increased. To address this issue, various cutting-edge solutions, such as radiation hardened sextuple cross coupled (RHSCC)-16T and DNU-completely-tolerant memory (DNUCTM) cells, have been proposed. While the RHSCC-16T cell is robust against SNU, it may be vulnerable to DNU. The DNUCTM cell is resistant to both SNU and DNU, but it remains susceptible to MNU. In this paper, we propose a radiation hardened read-stability and speed enhanced (RHRSE)-20T SRAM, which is immune to all potential cases of SNU, DNU, and MNU. Additionally, the proposed design demonstrates improvements in read and write delays compared to conventional SRAM designs. Experimental results confirm that the RHRSE-20T SRAM maintains stability under various charge levels for SEU, DNU, and MNU. The proposed integrated circuit is implemented in a 90-nm CMOS process and operates on a 1 V supply voltage, offering significant advantages for next-generation radiation-hardened memory applications.

Compact design of universal gates with non-aligned gate technology and assessment of its performance in a TCAD Environment

ABSTRACT This paper proposes a technology computer-aided design (TCAD) of a compact single-device NAND and NOR logic gates in 215 nm device length along with speed and power performance results. The universal gates are designed with non-aligned double gate technology, and this helps to reduce the transistor count, giving a compact design structure. The static characteristics and input pattern sensitivity of the NAND and NOR structures are investigated in this work. By using graphical method, the optimal supply voltage of the universal gates was determined. The optimal supply voltage of the NAND gate and NOR gate was 0.9 V and 0.84 V, respectively, at an input frequency of 1 GHz. Further, the device scalability of the proposed structures was analysed. When compared to the past work, the proposed NAND gate and NOR gate improves delay performance by 25.02% and 35.63%, respectively. Additionally, a reduction of 10% and 16% in its supply voltage is achieved. Therefore, the proposed gate has potential to operate at higher frequency with reduced supply voltage, making them suitable in circuit applications.

A low-power common-mode insensitive rail-to-rail dynamic comparator for ADCs

This paper presents a low-power, high-speed dynamic comparator with a rail-to-rail input common-mode (Vi,cm) range. The proposed comparator has high-speed performance throughout the 0-Vdd Vi,cm range, thus attributing common-mode insensitivity. This work introduces a merger of NMOS and PMOS dynamic pre-amplifiers with a modified latch to achieve the rail-to-rail Vi,cm operation. A novel activation clock logic is also proposed, activating only one pre-amplifier based on the Vi,cm value and ensuring low-power consumption and provides reduction of 17% in the energy per conversion as compared to the comparator without activation clock logic. The proposed comparator is designed using 65-nm CMOS technology with a 1.2 V supply voltage and is operating at 1 GHz frequency. We have presented the analytical models of the delay and offset which is verified with the rigorous post-layout simulation results. To validate the robustness of the proposed comparator, the PVT corner analysis with Monte Carlo simulation is also performed for different Vi,cm.

Influence of a new controlled voltage regulator on the current and voltage non-sinusoidality of a power supply system

This work evaluates the influence of a new controlled voltage regulator on the current and voltage non-sinusoidality in different sections of a power supply system during smooth (discrete) voltage regulation on the high-voltage side of a shop transformer. The MatLab software application was used to develop a block-modular model for a transformer substation with the proposed controlled voltage regulator and measurement modules. The developed model was used to investigate the current and voltage non-sinusoidality in different parts of a power supply system when stabilizing the voltage at the consumer end at a given level. The study was carried out using a shop transformer with a capacity of 1 MV∙A and a voltage of 6/0.4 kV under an active-inductive character of the load with the load current phase angle of φ=45 deg. The obtained results confirm that, due to the extended functional capabilities of the proposed technical solution, the voltage at consumers is maintained at a given level under high technical and economic performance. When the network voltage is reduced by 5% and the activeinductive load current is increased by 35%, the proposed device was shown to create voltage non-sinusoidality. The voltage non-sinusoidality value does not exceed the permissible domestic and international norms. In addition, the proposed device is capable of maintaining the voltage at the consumer end at a given level. The obtained integral characteristic of voltage stabilization shows that the application of the proposed technical solution instead of the existing mechanical voltage regulator of the “switching without excitation” type allows the nominal voltage at the busbar of the switchgear to be retained. Further research will investigate voltage stabilization at consumers with simultaneous compensation of reactive power for complex improvement of technical and economic indicators of power supply systems under the conditions of unstable supply voltage and load current.

INCAPE23-A Fully Differential Active Inductor with Cascode Current Mirror Using 0.18-um Technology for RF Frequency

This paper introduces a fully differential CMOS active inductor integrated with a cascoded current mirror, tailored for applications within the RF frequency range. The active inductor design is meticulously realized using CMOS 0.18-µm technology. The circuit implementation comprises a fully differential cross-coupled pair of transistors, strategically employed to impart negative feedback, thereby enhancing the quality factor (Q). The cascoded current mirror functions as a pivotal biasing component, facilitating control over the current source to modulate negative feedback and Q factor tuning. Simultaneously, two resistors integrated into the differential structure are crucial in managing the frequency spectrum. Simulation results substantiate a Q factor of 16k, coupled with an inductance of 14 nH, prominently achieved at 3 GHz frequency. Additionally, the objective of achieving a robust Q factor at 3.5 GHz, amounting to 500, is successfully realized. Noteworthy is the adaptability in achieving a frequency range spanning 2 GHz to 3.6 GHz by manipulating resistor values. Furthermore, the study observes that manipulation of supply voltage and current source enables the tuning of Q factor values from 70 to 16k. A performance assessment, juxtaposed with previously published works, underscores the viability of the proposed active inductor for applications within the gigahertz frequency range of RF.

INCAPE23-Design of Class E CMOS Power Amplifier with Integrated Active Inductor for 5G Applications

This paper presents a design of class E power amplifier (PA) with integrated active inductor for 5G applications. A high Q-factor active inductor (AI) is proposed utilizing CMOS 0.18-µm technology. A Gyrator-C based is employed to realize an active inductor with a double cascode resistive feedback configuration. The biasing voltage of 1.21 V, current source of 0.5 mA and supply voltage of 2.5 V is used. In order to obtain high efficiency, the proposed AI is implemented in a class E power amplifier by replacing on of the spiral inductors. According to the simulation results, the proposed AI can reach a high Q-factor of 50,000 and an inductance of 2.03 nH at 3.5 GHz. The power added efficiency (PAE) of CMOS class E PA with integrated AI, according to simulation result, is 72 % at 3.5 GHz. The intended PA's PAE was dramatically raised by the class E AI that was built.

Investigating the Influence of Protic Ionic Liquid on the Triboelectrical Properties of Trimethylolpropane Trioleate (TMPO)

Under triboelectric conditions, where tribocharging accelerates lubrication failure, lubricants with enhanced electrical properties are essential. Trimethylolpropane Trioleate (TMPO) oil, derived from esters that possess good lubricating properties and wear performance but is lacking in terms of electrical properties which can be further improved when blended with Ionic Liquid. This study blends 1 – 5 wt% of Protic Ionic Liquid (PIL) into TMPO and evaluate the frictional and wear performances of the blends under 1 – 2 A current conditions to understand the behaviour towards the tribological properties of different blends of material. Electric currents ranging around 1 – 2 A are implemented to the custom-designed ball-on-disc tribometer, with a constant 4.5 V voltage supply and the static resistance are measured. Mechanical wear properties are observed after the tribological test with different samples. The frictional properties of all concentrations of PIL in TMPO showed significant frictional improvements with 1%wt PIL showed 53% better results indicating improvements in frictional properties and wear performance under 2A current conditions, owing to its lowest film resistivity of 0.14 mΩ.

Effect of Voltage Supply Unbalance on Vibration of Three-Phase Induction Motor

Abstract The three-phase induction motor is the most popular electric motor used in industry. It has a simple and robust construction as well as a higher power density. It is a self-starting motor, therefore easier to start as compared to other types of electric motor. As the other benefit, a three-phase induction motor requires fewer maintenance measures. In order to maintain proper and continued operation, many parameters of a three-phase induction motor are constantly monitored. Among them is motor vibration. This is an important operation parameter frequently used to determine repair and maintenance needs to be taken on the motor. The vibration of a three-phase induction motor might be caused by mechanical as well as electrical problems. In this paper, the effect of magnitude unbalance of a three-phase voltage supply on the vibration of a three-phase induction motor is carefully investigated. To achieve this objective, two different laboratory experiments have been conducted. The first one is a three-phase induction motor supplied from a balance three-phase voltage supply. The second one is a three-phase induction motor supplied from an unbalance three-phase voltage supply. The unbalanced three-phase voltage supply condition is achieved by making the magnitude of one phase-voltage is 3%, 4%, and 5% lower than the magnitude of the other two phase-voltages. The vibration measurement is then taken in three different directions of the motor non-drive end (MNDE), i.e., horizontal (MNDEH), vertical (MNDEV), and axial (MNDEA). The experiment data show higher vibration in all directions, MNDEH, MNDEV, and MNDEA, as a load of the three-phase induction motor increases. Further, experiment data also show that higher vibration in all directions, MNDEH, MNDEV and MNDEA, is produced when unbalanced in magnitude voltage supply is higher

Simulation-based effective comparative analysis of neuron circuits for neuromorphic computation systems

The spiking neural networks (SNN) which are inspired by the human brain offers wider scope for application in the growth of neuromorphic computing systems due to their brain level computational capabilities, reduced power consumption, minimal data movement cost, and among other advantages. Spike-based neurons and synapses are the essential building blocks of SNN, and their efficient implementation is vital to its performance enhancement. In this regard, the design and implementation of spiking neurons have been the major focus among the researchers. In this paper, functioning of different leaky integrate fire (LIF)-based spiking neuron circuits like frequency adaptable CMOS-based LIF, resistor-capacitor-based (RC) LIF, and volatile memristor-based LIF are subjected to comparison. The work mainly focuses on revealing analysis of spike duration and amplitude, number of spikes produced during excitation period, threshold operation, field of application, and various other significant parameters of aforementioned neuron circuits. Extensive simulations of these circuits are carried out utilizing the Cadence Virtuoso simulation environment in order to validate their behavior. Further, a brief comparative analysis is executed considering into account the attributes like circuit complexity, supply voltage, firing rate, membrane capacitance, nature of input/output, refractory mechanism, and energy consumption per spike. This work seeks to assist researchers in selecting an appropriate LIF model to efficiently construct memristors and/or non-memristors based SNN for certain application.

Scalable, low-power and high-performance active-RC complex band-pass/low-pass filter with automatic frequency tuning applied to the Internet of Things

This article introduces a comprehensive 3rd Chebyshev active-RC complex band-pass/low-pass filter with an automatic cut-off frequency tuning circuit. The designed filter achieves 2 dB step gain control within the range of −6 dB–24 dB and 4 different bandwidth modes including low-pass modes and complex band-pass modes. A compact fully-differential (FD) amplifier with feedforward compensation and reverse pole splitting technique is used to meet the stringent filter's performance. The novel amplifier achieves an open loop gain of 62 dB and a maximum unity-gain bandwidth (UGB) of 732 MHz with VDD = 0.9 V and 0.32 mW of power dissipation. Using the proposed amplifier, the filter achieves the lowest power consumption reported in the literature for active-RC implementations and 30 % power reduction over similar active-RC filters. By employing an optimized solution for dynamic allocation of inter-stage gain, the filter achieves a maximum in-band-IIP3 of +25.7 dBm and an improvement of 2 dB. Also, an automatic frequency tuning scheme is used to eliminate the effect of process variation. The filter is fabricated in 22 nm CMOS process occupying 0.44 mm × 0.44 mm area and consuming 1.8 mW and 1.2 mW from 0.9 V supply voltage in Wi-Fi and BLE modes, respectively. The maximum figure of merit (FoM) is 142.6 dB/J. The RC tuning circuit has a precision of 1.5 % and covers a range of 20 %.

A wideband high-PSR OCL LDO using a gain-relaxed OTA featuring dynamic complex zeros frequency compensation

This article proposes an Output-Capacitor-Less (OCL) Low-Dropout (LDO) regulator with an assisted positive feedback loop technique, which mimics a negative resistance, along with a single common-gate stage. Conventional techniques utilize multistage high-gain OTA to achieve a high DC loop gain. However, such an OTA suffers from high power consumption and sophisticated frequency compensation mechanisms. Instead, the use of a single-stage relatively low-gain OTA helps to extend the bandwidth. Then, the overall DC loop gain is maximized by the proposal of a novel negative resistance circuit. To further improve the PSR, a bulk-driven ripple canceling path that is insensitive to process corners is proposed making the LDO suitable for high-PSR applications. Stability is another challenge in the design of OCL LDOs due to its associated complex poles. We propose a new frequency compensation technique by introducing two complex zeros to eliminate these complex poles. Hence, the overall stability is improved. Since these complex poles location vary from light to heavy loads, the proposed zeros dynamically change accordingly. Besides, this suggested mechanism has been analyzed using the generalized time-and-transfer constants (TTCs) circuit analysis technique. Under heavy load conditions, the suggested LDO has attained phase and gain margins of 62.8° and 29 dB, respectively. Moreover, Monte Carlo simulations along with process and temperature variations have been investigated to prove the reliability of such a frequency compensation technique. The proposed LDO has been implemented in 65 nm CMOS technology node with a short pass transistor length of 100nm. The simulation results reveals that the LDO draws 299.4μA of quiescent current under light load conditions and 296.8μA under heavy load conditions (including the bandgap voltage reference). The suggested LDO functions at 1.2V supply voltage, delivers 0.93V output voltage and can handle a load current up to 10mA with load regulation of 17μV/mA, line regulation of 2.22mV/V, and PSR of −48.7dB at low frequencies. The PSR at 1MHz is at least −32.5dB which is superior to the reported recent LDOs.

A 28 GHz balun‐first LNA with db‐linear 32 db gain range for 5 G applications

AbstractThis letter presents a 28 GHz balun‐first low noise amplifier (LNA) featuring a wide dB‐linear variable gain range. The architecture of LNA includes three‐stage cascode amplifiers. An integrated balun at the input stage provides RF ESD protection and converts a single‐ended signal to a differential one (S‐to‐D). A transformer‐based dual‐resonant matching network is designed and analyzed to achieve wideband performance. To realize a continuous dB‐linear variable gain range and consistent input/output matching, gain control is implemented in the second stage using a 5‐bit digital‐to‐analog converter (DAC) for a 32 dB gain range. The DAC can generate a nonlinear analog voltage to control the gate of the common‐gate transistor in the second cascode stage, inversely compensating for the nonlinear gain variations of the cascode amplifier. The LNA is fabricated in 65‐nm CMOS process with a core size of 0.154 mm². Measurement results exhibit a maximum gain of 33.5 dB and a minimum noise figure (NF) of 3.65 dB with a 3‐dB bandwidth of 23–29.5 GHz. The measured variable gain range is approximately 32 dB across 32 different gain states, with a linear gain step of ~1 dB per state and an IP1dB ranging from −6.5 dBm to −35.25 dBm. The power consumption is 35.4–48 mW from a 1.2 V supply voltage.

Charge pump-based PVT-resilient 45 nm CMOS dynamic comparator leveraging high speed and power efficiency

High-speed, low-power consumption, compact area, and high resolution are critical for analog /mixed signal applications. This article presents a novel design for a dynamic latch comparator that achieves exceptional speed, minimal power consumption, and a significantly reduced die area. The innovative comparator leverages a novel charge shared logic-based reset technique, which enables unparalleled speed and power efficiency. Rigorous simulations and analyses confirm that the delay time is drastically reduced compared to traditional dynamic latched comparators. The results clearly indicate that the proposed design exhibits high tolerance to PVT (process, voltage, and temperature) variations, making it highly suitable for mixed-signal applications. Designed and simulated using advanced 45 nm CMOS technology, the proposed circuit achieves an impressive delay of 18.5 ps and a remarkably low power consumption of 3.66 μW at a 1 V supply voltage and 1 GHz clock frequency.

Paper-based isotachophoretic preconcentration technique for low-cost determination of glyphosate.

Electrophoretic microfluidic paper-based analytical devices (e-µPADs) are promising for low-cost and portable technologies, but quantitative detection remains challenging. In this study, we develop a paper-based isotachophoretic preconcentration and separation method for the herbicide glyphosate as a model analyte. The device, consisting of two electrode chambers filled with leading and terminating electrolytes and a nitrocellulose strip as the separation carrier, was illuminated by a flat light source and operated with a voltage supply of 400V. Detection was accomplished using a simple camera. Colorimetric detection was optimized through competitive complexation between glyphosate, copper ions, and pyrocatechol violet as a dye. The buffer system was optimized using simulations, (i) ensuring the pH was optimal for the demetallation of the blue pyrocatechol violet-copper complex [PV] to the yellow free dye and (ii) ensuring the electrophoretic migration of glyphosate into the slower [PV] for the colorimetric reaction. A new data evaluation method is presented, analyzing the RGB channel intensities. The linear range was between 0.8 and 25µM, with a LOD of approximately 0.8µM. The ITP separation preconcentrated glyphosate by a factor of 820 in numerical simulations. The method may be applied to control glyphosate formulations, especially in developing countries where herbicide sales and applications are poorly regulated.

A compact and tunable active inductor-based bandpass filter with high quality factor for Wireless LAN applications

A fully-differential compact and tunable second-order bandpass filter (BPF) with high quality factor using a novel active inductor (AI) has been proposed for 3.6 GHz WLAN applications. The proposed AI employs a differential amplifier as a feedforward transconductor and a common-source (CS) transistor as a feedback transconductor in a symmetrical configuration. The combination of a cascode scheme and a resistor in the feedback path enhances the quality factor of the AI, thereby increasing the mid-band gain of the BPF. In order to achieve independent tuning of both the center frequency and mid-band gain of the BPF, a varactor capacitor is utilized. The proposed second-order BPF is designed with a center frequency and a bandwidth of 3.675 GHz and 10 MHz, respectively. Post-layout simulation, process corner, and temperature sweep analysis results are conducted with 65 nm CMOS technology at 1.2 V supply voltage. The proposed filter has a tuning range of 3.655–3.695 GHz and attains a mid-band gain of 67.5 dB, a noise figure of 14.5 dB, and a 1-db compression point of −12.39 dBm. Additionally, the BPF consumes a DC power of 1.22 mW and occupies an active area of only 8.85 μm × 10.3 μm.

Selective-Area Growth of InGaAs Nanowires on SOI and the Vertical Transistor Application

The gate-all-around (GAA) structure avoids the problems inherent in miniaturizing field-effect transistors (FETs), such as off-state leakage current and short-channel effects. Among GAA structures, vertical GAA (VGAA) structures are expected as promising building blocks for future three-dimensional integrated circuit applications. The vertical III-V nanowires (NWs) on Si are expected as the fast channel materials for the VGAA structures on Si platforms. Thus, the combination of the VGAA structure with III-V NWs on Si significantly enhances on-state current while maintaining good gate controllability under low supply voltage. In addition, III-V NWs/Si tunnel junctions, which are formed by the direct integration of vertical III-V NWs on Si, can be utilized as VGAA tunnel FETs (TFETs) for low-power switch. Here we report on direct integration of vertical InGaAs NWs on silicon-on-insulator (SOI) substrates by selective-area growth and demonstrations of InGaAs NW-channel VGAA transistors (FETs and TFETs) on SOI.

Exploiting Spatial Ionic Dynamics in Solid-State Organic Electrochemical Transistors for Multi-Tactile Sensing and Processing.

The human nervous system inspires the next generation of sensory and communication systems for robotics, human-machine interfaces (HMIs), biomedical applications, and artificial intelligence. Neuromorphic approaches address processing challenges; however, the vast number of sensors and their large-scale distribution complicate analog data manipulation. Conventional digital multiplexers are limited by complex circuit architecture and high supply voltage. Large sensory arrays further complicate wiring. An 'in-electrolyte computing' platform is presented by integrating organic electrochemical transistors (OECTs) with a solid-state polymer electrolyte. These devices use synapse-like signal transport and spatially dependent bulk ionic doping, achieving over 400 times modulation in channel conductance, allowing discrimination of locally random-access events without peripheral circuitry or address assignment. It demonstrates information processing from 12 tactile sensors with a single OECT output, showing clear advantages in circuit simplicity over existing all-electronic, all-digital implementations. This self-multiplexer platform offers exciting prospects for circuit-free integration with sensory arrays for high-quality, large-volume analog signal processing.