Selective-Area Growth of InGaAs Nanowires on SOI and the Vertical Transistor Application

Abstract

The gate-all-around (GAA) structure avoids the problems inherent in miniaturizing field-effect transistors (FETs), such as off-state leakage current and short-channel effects. Among GAA structures, vertical GAA (VGAA) structures are expected as promising building blocks for future three-dimensional integrated circuit applications. The vertical III-V nanowires (NWs) on Si are expected as the fast channel materials for the VGAA structures on Si platforms. Thus, the combination of the VGAA structure with III-V NWs on Si significantly enhances on-state current while maintaining good gate controllability under low supply voltage. In addition, III-V NWs/Si tunnel junctions, which are formed by the direct integration of vertical III-V NWs on Si, can be utilized as VGAA tunnel FETs (TFETs) for low-power switch. Here we report on direct integration of vertical InGaAs NWs on silicon-on-insulator (SOI) substrates by selective-area growth and demonstrations of InGaAs NW-channel VGAA transistors (FETs and TFETs) on SOI.