Supply Voltage Scaling Research Articles

A new write assist technique for SRAM design in 65 nm CMOS technology

In this paper, a new write assist technique for SRAM arrays is proposed. In this technique, to improve the write features of the SRAM cell, a negative voltage is applied to one of the bitlines in the SRAM cell while another bitline is connected to a boosted voltage. Improved write features are attributed to the boosting scheme from both sides of the SRAM cell. This technique is applied to a 10T-SRAM cell with transmission-gate access devices. The proposed design gives 2.7×, 2.1× faster write time, 82% and 18% improvement in write margin compared with the standard 8T-SRAM cell with and without write assist, respectively. All simulations have been done in TSMC 65nm CMOS technology. The proposed write assist technique enables 10T-SRAM cell to operate with 24% lower supply voltage compared with standard 8T-SRAM cell with negative bitline write assist. Due to the improved supply voltage scalability a 33% leakage power reduction is achieved.

A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS

A PSK receiver (RX) is proposed that employs a digital-intensive architecture based on sub-sampling, Q-enhancement, and digital IF to enable low-power (1.3 mW) and low-voltage (0.6 V) operation. Implemented in 65 nm CMOS, this work is compatible with the IEEE 802.15.6 (WBAN) narrowband physical layer specification and achieves -91 dBm and -96 dBm sensitivity at 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> BER for π/4-DQPSK and π/2-DBPSK modulation respectively. The proposed highly digital architecture and supply voltage scaling lead to a 3x improvement in RX energy efficiency and minimize silicon area consumption (~ 0.35 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 65 nm CMOS) while achieving state-of-the-art sensitivity. While this implementation focuses on WBAN demodulation, the proposed architecture and circuit techniques are generally applicable to RX targeting ultra-low power consumption for sensor networks.

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) or even to the subthreshold (sub- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) domain is a commonly used, efficient technique to reduce both leakage power and active energy dissipation. On the other hand, emerging CMOS-compatible device technologies such as Resistive Memories (ReRAMs) enable non-volatile, on-chip data storage and zero-leakage sleep periods. For the first time, we present and compare ReRAM-based Non-Volatile Flip-Flop (NVFF) topologies which are optimized for low-voltage operation (including near-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and sub-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> operation). Three low-voltage NVFF circuit topologies are proposed and evaluated in terms of energy dissipation and reliability. Using topologies with two complementary programmed ReRAM devices, Monte Carlo simulations accounting for parametric variations confirm reliable data restore operation from the ReRAM devices at a sub- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> voltage as low as 400 mV. A topology using a single ReRAM device exhibits lower write energy, but requires a near-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> voltage for robust read. Energy characterization is performed at nominal, near- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , and sub- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> supply voltages. The minimum energy point is reached for near- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> read operation with a total read+write energy of 735 fJ.

A 290 mV Sub-V(T) ASIC for Real-Time Atrial Fibrillation Detection.

A real-time detector for episodes of atrial fibrillation is fabricated as an application specific integrated circuit (ASIC). The basis for detection is a set of three parameters for characterizing the RR interval series, i.e., turning point ratio, root mean square of successive differences, and Shannon entropy. The developed hardware architecture targets ultra-low voltage operation, suitable for implantable loop recorders with ultra-low energy requirements. Algorithmic and architectural optimizations are performed to minimize area and energy dissipation, with a total area footprint reduction of 44%. The design is fabricated in 65-nm CMOS low-leakage high-threshold technology. Measurements with aggressively scaled supply voltage (VDD) in the subthreshold (sub-VT) region show energy savings of up to 41 X when operating at 1 kHz with a VDD of 300 mV compared to a nominal VDD of 1.2 V.

Development of III-Sb Technology for p-Channel MOSFETs

Alternative channel materials with superior transport properties over conventional silicon based systems are required for supply voltage scaling in CMOS circuits. Group III- Sb 's are a candidate for high mobility p-channel applications due to a low hole effective mass, large injection velocity in scaled devices and the ability to achieve enhanced hole mobility in strained quantum wells (QW). Multiple challenges in antimonide MOSFET development are assessed and developed technologies were implemented into p-channel MOSFET fabrication with a low thermal processing budget of 350°C. These challenges include growth of “bulk” GaSb and bi-axial compressively strained In x Ga 1-x Sb QW channels on lattice mismatched GaAs substrates, reduction of interface trap state density (Dit) at the III- Sb /high-k oxide interface and avoiding ion implanted source and drain contacts with high temperature activation annealing. A “self-aligned” single mask p-channel MOSFET fabrication process was developed on buried In 0.36 Ga 0.64 Sb QW channels using intermetallic source and drain contacts. The first “gate-last” MOSFET process on In 0.36 Ga 0.64 Sb QW channels with pre-grown epitaxial p++- GaSb contacts is demonstrated. InAs has been proven to be an excellent etch stop layer when using an optimized tetramethylammonium hydroxide (TMAH) etch of p++- GaSb to prevent InGaSb QW damage.

Current Status of Slurries and Cleans for CMP of III-V Device Fabrications – A Critical Review

With the growth of cloud computing market, the need for logic and memory chips for data centers have been steadily growing which require low power and high performance. Another area of growing semiconductor application is mobile products which require increasingly higher performance without sacrificing power. The above two requirements can only be achieved by scaling supply voltage (Vdd). III-V materials enable Vdd scaling to address power without sacrificing performance due to the very high electron injection velocity at virtual source compared to Si. For example, Vinj (InGaAs) > 2Vinj (Si) at less than half VDD. The development at Intel on InGaAs and at IMEC on Ge based FinFET structures have made it possible to conceive new integration schemes[1]. In order to enable such CMOS fabrication, development of CMP (Chemical Mechanical Planarization) slurry, post CMP clean and modification of the presently available process tools need to be done. While new slurries and cleans will be needed to planarize III-V film layer(s) without compromising the film composition (and functionality), modification of the process tool will be needed to address potential release of toxic waste water into the waste stream after planarization. In this paper, the status of development of CMP processes, slurries and post CMP cleans will be reviewed and the critical needs to enable for the future III-V device integration will be analyzed.

Dynamic Current Mode Logic Realization of Digital Arithmetic Circuits

In this paper, we realize a high performance arithmetic circuits which is faster and have lower power consumption using a new dynamic logic family of CMOS and to analyze its performance for arithmetic circuits. This new dynamic logic family is known as Dynamic Current Mode Logic (DyCML). DyCML circuits combine the advantages of MOS current mode logic (MCML) circuits with those of dynamic logic families to achieve high performance at a low-supply voltage with low-power dissipation. A major advantage of the DyCML is the dynamic current source, which achieves smaller delays compared to the basic MCML circuits. Other advantages inherited from MCML are high performance and robustness to supply voltage scaling. DyCML gates reduce power dissipation by reducing the output voltage swing. We compare a set of arithmetic circuits implemented in Dynamic Current Mode Logic with the other dynamic logic styles. Simulation and test results show that DyCML circuits are superior to DDCVS logic styles in terms of power dissipation. A 2-bit multiplier, full adder & xor/xnor gate in DyCML style is fabricated in 180nm CMOS technology. 2-bit multiplier and a full adder dissipate 145.1 µW and 55.14 µW respectively at 40 MHz for a voltage swing of 1.2V in DyCML style.

Soft-Error Performance Evaluation on Emerging Low Power Devices

Radiation-induced single-event upset (SEU) has become a key challenge for cloud computing. The proposed introduction of low bandgap materials (Ge, III-Vs) as channel replacement and steep switching devices for low-voltage applications may induce radiation reliability issues due to their low ionization energy and device architecture. In this paper, the soft-error generation and propagation in Si FinFET, III-V FinFET, and III-V Hetero-junction tunnel FET (HTFET) are investigated using device and circuit simulation. III-V FinFET shows enhanced charge collection compared with Si FinFET, whereas HTFET shows significant reduction of the bipolar gain effect and charge collection. Soft-error rate (SER) evaluation methodology has been proposed for these emerging devices based on the critical LET extraction. SRAM bit flip, electrical masking effect, and latching window masking effect have been analyzed with supply voltage scaling. The SER evaluation of SRAM and logic shows that HTFET-based circuits are promising for radiation resilient ultra-low power applications. III-V FinFET shows increased SER for SRAM for ${\rm V}_{\rm DD}$ range of 0.3–0.8 Vand reduced logic SER below 0.5 V compared with Si FinFET.

Current Status of Slurries and Cleans for CMP of III-V Device Fabrications – a Critical Review

With the growth of cloud computing market, the need for logic and memory chips for data centers have been steadily growing which require low power and high performance. Another area of growing semiconductor application is mobile products which require increasingly higher performance without sacrificing power. The above two requirements can only be achieved by scaling supply voltage(Vdd).III-V materials enable Vdd scaling to address power without sacrificing performance due to the very high electron injection velocity at virtual source compared to Si. For example, Vinj (InGaAs) > 2 Vinj (Si) at less than half VDD. The development at Intel on InGaAs and at IMEC on Ge based FinFET structures have made it possible to conceive the integration scheme such as depicted in http://www.compoundsemiconductor.net/csc/features-details/19732136/Uniting-III-Vs-and-germanium-for-CMO.html . In order to enable such CMOS fabrication, development of CMP slurry, post CMP clean and modification of the presently available process tools need to be done. While new slurries and cleans will be needed to planarize III-V film layer(s) without compromising the film composition (and functionality), modification of the process tool will be needed to address potential release of toxic waste water into the the waste stream after planarization.At this time, published results show some academic works in addressing various issues related to CMP of III-V materials but there are not many reports in the public domain from the industry to address the need which is essential to successfully integrate CMP as an enabling step in the manufacturing of III-V CMOS devices.In this paper, the status of development of CMP processes, slurries and post CMP cleans will be reviewed and the critical needs to enable for the future III-V device integration will be analyzed.

Study of Hetero-Tunneling Gfet with an Ultra-Shallow Pocket Junction

Because the subthreshold swing (SS) of a MOSFET is larger than 60mV/dec at room temperature, its threshold voltage cannot be very small. This limits the scaling of power supply voltage (VDD) and the reduction of power density. Tunnel field effect transistor (TFET) can overcome this fundamental limitation, which mechanism is based in the band-to-band tunneling (BTBT). However, the drive current in TFETs is significantly lower than in MOSFETs owing to tunneling resistance which arises due to carrier tunneling. Achieving large drive current at low VDDhas been a great challenge. Green transistor (gFET) is a novel structure TFET with a heavily doped pocket in the gate-source overlap region. The pocket junction can provide large and uniform field over a substantial area, which can offer larger drive current and steeper subthreshold swing as compared to conventional tunneling transistors. And, when the pocket junction depth becomes shallower, the drive current will be improved significantly. But study reveal that gFET is only suitable for orepation at 0.5V. To further reduce Vdd, even smaller bandgap material may be employed.In this study, a hetero-tunneling gFET with an ultra-shallow pocket junction has been developed, as shown in Fig.1. The gFET was fabricated in a 8inch (100) silicon (Si) substrate, as shown in Fig.2. After LOCOS formation, silicon-germanium (Si1-xGex) and Si cap layer were grown on Si substrate using selective epitaxy. After source implantation, an ultra-shallower pocket is formed by using of the Ge preamorphization implantation (PAI), ultra low energy implantation and spike annealing. Si1-xGex and Si have different lattice constant. Biaxially strained will be formed in the Si1-xGex/Si heterostructures. The biaxial strain will shift the conduction and valance band energy levels of semiconductors and obtain ultra low effective tunneling bandgaps, which is helpful to get smaller tunneling length and barrier height. The same current can be obtained at lower gate voltage and drain voltage. The hetero-tunneling gFET integrated with the ultra-shallow pocket junction exhibits good electrical characteristics, such as smaller subthreshold swing, higher Ion/Ioff ratio and so on.

Tunnel FET technology: A reliability perspective

Tunneling-field-effect-transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage (VDD) scaling in ultra-low power, energy efficient computing, due to its sub-60mV/decade sub-threshold slope (SS). Given its unique device characteristics such as the asymmetrical source/drain design induced uni-directional conduction, enhanced on-state Miller capacitance effect and steep switching at low voltages, TFET based circuit design requires strong interactions between the device-level and the circuit-level to explore the performance benefits, with certain modifications of the conventional CMOS circuits to achieve the functionality and optimal energy efficiency. Because TFET operates at low supply voltage range (VDD<0.5V) to outperform CMOS, reliability issues can have profound impact on the circuit design from the practical application perspective. In this review paper, we present recent development on Tunnel FET device design, and modeling technique for circuit implementation and performance benchmarking. We focus on the reliability issues such as soft-error, electrical noise and process variation, and their impact on TFET based circuit performance compared to sub-threshold CMOS. Analytical models of electrical noise and process variation are also discussed for circuit-level simulation.

A 1–13 Gbps tunable optical receiver with supply voltage scaling

A 1–13 Gbps tunable optical receiver with supply voltage scaling

A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX

This paper process a novel design for low power 1-bit CMOS full adder using XNOR and MUX, with reduced number of transistors using GDI cell. The circuits were simulated with supply voltage scaling from 1.2V to 0.6V &amp;0.6V to 0.3V. To achieve the desired performance of power delay product, area, capacitance the transistors with low threshold voltage were used at critical paths and high threshold voltage at non critical paths. The results show the efficiency of the proposed technique in terms of power consumption, delay and area.

An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library

Pulse-triggered flip-flops are candidates to improve pipeline speed, although flip-flop robustness and system timing closure are challenging in a wide range of supply voltages. Pulse-triggered flip-flops usually have specific structures and transistor sizes to optimize performance. The topology, transistor size, and threshold voltage of the flip-flop make the timing characteristics sensitive to the supply voltage. The transparent windows generated and required in a pulse-triggered flip-flop may have mismatch under supply voltage scaling, which is likely to result in functional and system timing failures. Therefore, this brief proposes an adaptive pulse-generating method to fit the transparent window required in situ. Process variations and intrinsic transistor driving-strength mismatches are considered. The proposed structure improves the robustness of pulse-triggered flip-flops and promises this high-speed clocked element for wide-voltage-range operations. A normalized timing metric is also introduced to characterize flip-flops and help timing tradeoffs in wide-voltage-range operations.

High-Performance and Robust SRAM Cell Based on Asymmetric Dual-$k$ Spacer FinFETs

This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET) structure using a dual- k spacer. Asymmetric dual-spacer at source shows excellent gate control over the channel due to increase in the outer fringe field at gate/source underlap. Hence, this structure exhibits a superior short-channel effect metric over the conventional/single-spacer underlap FinFET. The proposed asymmetric structure enhances static random access memories (SRAMs) performance in terms of robustness, access times as well as leakage power during the hold, read, and write operations. The hold static noise margin and write margin increases by 5.16% and 5.66%, respectively. The read stability enhances by 13.75% and 19.35% over conventional FinFET SRAM circuit. Furthermore, the leakage power reduces by 60%, and write access time improves by 23.63%. Compared with conventional FinFET-based SRAM, same bit-cell area and read delay are associated with the proposed structure. Supply voltage scalability on SRAM design metrics is also investigated. In addition to SRAM application, underlap length, lateral source/drain doping gradient, and the high- k spacer width are optimized for high-performance digital applications.

Limits of Parallelism and Boosting in Dim Silicon

Supply-voltage scaling has stagnated in recent technology nodes, leading to so-called dark silicon. To increase overall chip multiprocessor (CMP) performance, it is necessary to improve the energy efficiency of individual tasks so that more tasks can be executed simultaneously within thermal limits. In this article, the authors investigate the limit of voltage scaling together with task parallelization to maintain task completion latency while reducing energy consumption. Additionally, they examine improvements in energy efficiency and parallelism when serial portions of code can be overcome through quickly boosting a core's operating voltage. When accounting for parallelization overheads, minimum task energy is obtained at near-threshold supply voltages across six commercial technology nodes and provides 4× improvement in overall CMP performance. Boosting is most effective when the task is modestly parallelizable but not highly parallelizable.

A Resolution-Reconfigurable 5-to-10-Bit 0.4-to-1 V Power Scalable SAR ADC for Sensor Applications

A power-scalable SAR ADC for sensor applications is presented. The ADC features a reconfigurable 5-to-10-bit DAC whose power scales exponentially with resolution. At low resolutions where noise and linearity requirements are reduced, supply voltage scaling is leveraged to further reduce the energy-per-conversion. The ADC operates up to 2 MS/s at 1 V and 5 kS/s at 0.4 V, and its power scales linearly with sample rate down to leakage levels of 53 nW at 1 V and 4 nW at 0.4 V. Leakage power-gating during a SLEEP mode in between conversions reduces total power by up to 14% at sample rates below 1 kS/s. Prototyped in a low-power 65 nm CMOS process, the ADC in 10-bit mode achieves an INL and DNL of 0.57 LSB and 0.58 LSB respectively at 0.6 V, and the Nyquist SNDR and SFDR are 55 dB and 69 dB respectively at 0.55 V and 20 kS/s. The ADC achieves an optimal FOM of 22.4 fJ/conversion-step at 0.55 V in 10-bit mode. The combined techniques of DAC resolution and voltage scaling maximize efficiency at low resolutions, resulting in an FOM that increases by only 7x over the 5-bit scaling range, improving upon a 32x degradation that would otherwise arise from truncation of bits from an ADC of fixed resolution and voltage.

P.16: Dynamic Supply Voltage Scaling of Pixel Circuits for Static Power Reduction in AMOLEDs

AbstractOne‐dimensional (1‐D) Dynamic supply Voltage Scaling (DVS) scheme with image distortion compensation is proposed for reducing the static power consumption in AMOLED displays. A hybrid simulation platform combining MATLAB and circuit simulator HSPICE was built for the study. By applying the DVS scheme to both static images and video streams, it is shown significant power saving can be achieved (&gt;40% for the test video streams) without sacrifice of the image or video quality.

Design and Performance Comparison of 6-T SRAM Cell in 32nm CMOS, FinFET and CNTFET Technologies

In most of the digital circuits, CMOS based design is allowed to be used in practice. Generally, CMOS stands for Complementary Metal Oxide Semiconductor Field Effect Transistor, that is, considered to be as combination of both PMOS as well as NMOS. In CMOS based design, symmetry should be followed in circuit operation. Most of the complex circuits are allowed to design in CMOS, however, there are several drawbacks present in this complementary based design. Also, SRAM cell read stability and write-ability are major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and supply voltage scaling. Therefore, it is necessary to find alternative way suitable for particular design, instead of CMOS. Most of the modern design is based on Carbon nanotube FET or FinFET because of its superior properties interms of power consumption, leakage power, delay etc. The objective of this work mainly focus on designing 6-T SRAM cell in 32nm CMOS, CNTFET as well as FinFET and finally, to compare the parameters such as average power, delay and leakage current.

A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O Transceiver in 65 nm CMOS

A low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase filter. The output driver voltage swing is accurately controlled from 100–200 ${\rm mV}_{\rm ppd}$ using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range. In the transmitter clocking circuitry, per-phase duty-cycle and phase-spacing adjustment is implemented to allow adequate timing margins at low operating voltages. Fabricated in a general purpose 65 nm CMOS process, the transceiver achieves 4.8–8 Gb/s at 0.47–0.66 pJ/b energy efficiency for ${\rm V}_{\rm DD}=0.6$ –0.8 V.