Supply Voltage Noise Research Articles

On-Chip Quantization- and Correlation-Robust Jitter Measurement for Low Phase Noise and High Frequency Oscillators

For on-chip oscillator phase noise characterization and monitoring a common technique is the measurement of the equivalent cycle-to-cycle jitter. In this letter we show that the quantization introduced to the recorded jitter by the measurement with a time-to-digital converter can be prohibitive for calculating the phase noise, especially at high oscillation frequencies and for spectrally pure oscillators. A second drawback of this method is that supply voltage noise can mask the phase noise due to intrinsic device noise. To avoid these limitations, we investigate an approach where the oscillator under test is compared to an identical replica. The resulting time difference measurements are introduced as delta jitter. The validity of the method is proven in simulation and measurement of an on-chip jitter measurement macro designed in 16 nm FinFET CMOS technology. The measurement results indicate both robustness against quantization error and a self-canceling of correlated influences on phase noise in delta jitter measurements.

Adaptive backstepping controller design for DC/DC buck converter optimised by grey wolf algorithm

AbstractA Lypunov‐based Adaptive Backstepping Control (ABSC) approach is designed for a power Buck converter. This strategy is an advanced version of the Backstepping method utilising Lyapunov stability function to reach a higher stability and a better disturbance rejection behaviour in the practical applications. In addition, to reduce the computational burden and increase ease of implantation, Black‐box technique is considered assuming no accurate mathematical model for the system. Nonetheless, in real‐time environments, disturbances with wider ranges including: supply voltage variation, parametric variation, and noise can negatively impact the operation of this method. To compensate for this problem, the gains of the controller should be tuned again for better adaptability with the working condition. Therefore, to satisfy this need and enhance the controller's performance, a metaheuristic algorithm is applied in the control scheme called Grey Wolf Optimisation (GWO) algorithm. GWO is a well‐behaved nature‐inspired algorithm with faster decision‐making dynamics along with more accuracy over different optimisation algorithms. To better elaborate the merits of this approach, conventional BSM and PSO‐based PID schemes are also designed and tested in different situations.

Analysis of Pre-Driver and Last-Stage Power-Ground-Induced Jitter at Different PVT Corners.

This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct DC supply voltages at the pre-driver (i.e., /) and last stage (i.e., ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions.

A Supply Voltage Noise Immunity Enhancement Design for High-Voltage Gate Driver IC Based on Bootstrap Circuit

One important design aspect of a high-voltage gate driver integrated circuit (HVIC) is safety because the failure operation such as latch-on failure may cause severe damage to the system and may pose physical harm to the user. In the HVIC, a noise on the high-side supply voltage was considered as the main source of failure operation, however, a low-side supply voltage noise also can cause latch-on failure to the high-side circuitry. In this brief, the failure caused by the high-side as well as low-side supply voltage noise is analyzed, and a supply voltage noise immunity enhancement design for HVIC is described. The HVIC has been implemented in a 1.2 μm 600 V BCDMOS process. The proposed design shows a latch-on free operation from the various slope of the supply voltage drops while the conventional design shows shoot-through failure by latch-on failure. The approach is well suited for the harsh supply voltage environment such as the automotive application.

Low power and low phase noise VCO with dual current shaping for IoT applications

In this paper, two low phase noise and power consumption VCO circuits, which are suitable for Internet of things (IoT) applications, are proposed. In the first structure, in order to have more control of the current consumption, the current shaping technique is used in the PMOS and NMOS biasing circuit. In the second structure, for increasing the oscillation amplitude and reducing the phase noise, independent biasing for the NMOS section is used. In both structures, to increase the frequency tuning range (FTR), without using a capacitor bank, the varactor is used in the biasing structure. In the first structure the supply voltage, output frequency, power consumption, and phase noise are 0.8 V, 2.44 GHz, 0.37 mW, and -117.5 dBc/Hz, respectively, but in the second structure, the supply voltage, output frequency, power consumption, and phase noise are 0.8 V, 2.44 GHz, 0.62 mW, and -120 dBc/Hz, respectively. It should be noted that the two structures are designed and simulated in 65-nm CMOS technology. Finally, the results show that the figure-of-merit for the first and second structures is --190 dBc/Hz and --190.2 dBc/Hz, respectively.

Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power Management

In today's manycore processors, the energy loss of more than 20% may result from inherent inefficiencies of conventional power delivery system (PDS) design. By stacking multiple voltage domains in series to lower the step-down conversion ratio of the off-chip voltage regulator module (VRM) and reduce the energy loss along the path of the power delivery network (PDN), voltage stacking (VS) offers a novel alternative power delivery technique to fundamentally improve power delivery efficiency (PDE). However, VS suffers from aggravated supply voltage noise from the current imbalance, which hinders its adoption. In this article, we investigate practical VS implementation in manycore processors to improve PDE and achieve reliable performance, while maintaining compatibility with advanced power management techniques. We first present the system configuration of a voltage-stacked manycore processor. We then systematically characterize supply voltage noise in VS, identify global, and residual differential currents as its dominant contributors, and calculate the possible worst supply voltage noise. We next propose a hybrid voltage regulation solution, based on a charge-recycling off-chip voltage regulator and distributed integrated voltage regulators, to mitigate supply voltage noise effectively. We also study the compatibility of VS with higher-level power management techniques. Finally, the performance of a voltage-stacked GPU system is comprehensively evaluated. The simulation results show that our approach can achieve 93.5% PDE, reducing the power loss by 13.6% compared to conventional single-layer PDS.

A Multicore Chip Load Model for PDN Analysis Considering Voltage–Current-Timing Interdependency and Operation Mode Transitions

Power consumption and current fluctuation are continuously increasing in modern multicore systems. Such current flow may cause severe supply noise via off-chip and on-chip power delivery networks (PDN). Unexpected noise impacts the chip delay performance or even causes malfunction. In traditional practice, PDN designers assume a simple current source-based chip load, but it is often oversimplified, where the load current is modeled only for one or a few operation modes, and it is constant irrelevant to supply noise. In this paper, we propose a new chip load model that enables even off-chip PDN designers to assess the noise impact on circuit performance and use realistic current profile under supply voltage noise. We also integrate a control signal interface so that the model can switch the processor operation modes for finding unexpected noise behavior in design time and pursuing robust PDN design. Experimental results show that the proposed model mostly described by Verilog-A reproduces the current profile, current peak, and timing data well even while it achieves over $300\times $ run-time reduction compared to a transistor-level model. We also experimentally demonstrate that a land-side capacitor is helpful to improve processor timing performance in our test case.

Fractional Order High Pass Filter Based on Operational Transresistance Amplifier with Three Fractional Capacitors of Different Order

Design, realization and performance evaluation of fractional order high pass filter based on Operational Transresistance Amplifier (OTRA) using three fractional elements of different order α, β, γ are presented in this paper. The projected circuit uses a single active current mode device i.e. OTRA and utilizes fractional capacitors of varying orders to boost the design flexibility. The design equations for fractional order high pass filter are computed from the transfer function. The paper elaborates the impact of fractional order elements of varying order on the frequency response of the filter. Subsequently, the sensitivity and stability of the transfer function of the proposed filter are also analyzed. The potential usefulness of the proposed filter is additionally incontestable through the Total Harmonic Distortion (THD), Power Supply Rejection Ratio (PSRR), Temperature sweep, Corner, Supply Voltage variation and Noise Analysis. It has been observed that the proposed pass filter in fractional domain supported OTRA provides greater flexibility in controlling the magnitude characteristics.

Tunable CMOS Active Inductor Using Widlar Current Source

A novel tuning principle for simple gyrator-based CMOS active inductor (AI) circuit is presented. The method makes use of Widlar current source to enhance the quality factor. The simulation of the proposed AI provides a maximum quality factor of 1819 at 2.88[Formula: see text]GHz. The AI shows the inductive bandwidth of 1.66[Formula: see text]GHz to 3.16[Formula: see text]GHz and power consumption of 6.87[Formula: see text]mW. The other characterization factors such as linearity, supply voltage sensitivity and noise analysis are discussed. The performance of the tunable AI using Widlar current source are compared with the same using a simple current mirror. An AI using a conventional current mirror (CCM) and Widlar current source have been implemented in the 0.18[Formula: see text][Formula: see text]m CMOS technology.

A Carry Chain-Based ADMFC Design on an FPGA for EMI Reduction and Noise Compensation

An all-digital multi-frequency clocking (ADMFC) circuit is proposed to reduce electromagnetic interference (EMI) on a field-programmable gate array (FPGA) architecture, while supporting dynamic adaptation to voltage noises. The proposed ADMFC uses dedicated high-speed carry chain paths in an FPGA to finely adjust the clock frequency by controlling the number of carry propagations on the carry chain logics (CARRY4 cells) in the delay line of a ring oscillator. Moreover, supply voltage variation and noise caused by circuit switchings can be compensated by dynamically adjusting the length of ripple carry propagations on the cascaded CARRY4 cells in response to the detected voltage variation. Finally, a selectable modulation profile is devised to provide a much suitable profile between two different profiles at run-time for the given noise constraints and working environment of a chip. Measurement results show that at the frequency of 44.6[Formula: see text]MHz, the ADMFC can obtain 17[Formula: see text]dB and 19.4[Formula: see text]dB EMI attenuations with a 7.5% spreading ratio when using triangular and sawtooth profiles, respectively. The proposed ADMFC is suitable for applications such as biological sensor nodes or IoT related systems which typically operate at a low-frequency band.

A 0.65-V process variation and supply noise insensitive ring VCO

ABSTRACTA low-voltage feedforward ring voltage-controlled oscillator (FRVCO) withstanding process variation and supply-voltage noise is proposed in this paper. In this design, the variation of transistors’ threshold voltages and supply voltage noise are detected by a compensating voltage generated circuit, and the load capacitance of the FRVCO is tuned by the compensating voltage to reduce the variation of oscillating frequency. Simulation results demonstrate that the centre oscillating frequency difference between ‘FF’ and ‘SS’ corners is reduced from 38.3% to 1.5% by tuning the voltage from 0 to 650 mV. Moreover, with a supply voltage change of ±0.5%, the frequency variation is smaller than ±0.06%. The 0.65-V 600-MHz FRVCO has been fabricated using the TSMC 130-nm CMOS process.

Performance Enhancement of a Time-Delay PUF Design by Utilizing Integrated Nanoscale ReRAM Devices

Currently the semiconductor industry is in search of a Physically-Unclonable-Function (PUF) implementation, which combines high reliability and uniqueness with low area and power consumption. The characteristics of emerging nanoscale Resistive Random Access Memory (ReRAM) devices fulfill most of these properties, as they exhibit inherent variability with low area consumption. Of particular interest is that the resistive states of ReRAM devices show a strong dependence on the distribution of grain boundaries within the device, which leads to variability in total device resistance. In this work we transform the classic CMOS time-delay PUF (TD-PUF) utilizing integrated nanoscale ReRAM devices to achieve better performance metrics including uniqueness and reliabilitiiy. The enhanced design exploits the property of high resistance variability of ReRAMs for the design of a ReRAM based delay stage that exhibits excellent uniqueness. Accurate simulation and characterization of the proposed PUF was achieved by extracting resistance values, temperature dependence and usage stress of ReRAM devices fabricated in-house and their application in the proposed TD-PUF are discussed. A 24 stage time-delay PUF utilizing 48 ReRAM devices was simulated and results show excellent reliability with respect to environmental parameters. A temperature range of 0 to 125°C was simulated and an optimum reliability was observed at 0.79 V. A supply voltage noise of ±30 mV had no impact on the uniqueness and reliability. The proposed design was compared against two pure CMOS implementations of a TD-PUF. The comparison was performed with respect to the aforementioned metrics and under the same environmental conditions, showing up to 5 times increase in performance.

Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor

This paper presents a power delivery monitor (PDM) peripheral integrated in a flip-chip packaged 28 nm system-on-chip (SoC) for mobile computing. The PDM is composed entirely of digital standard cells and consists of: 1) a fully integrated VCO-based digital sampling oscilloscope; 2) a synthetic current load; and 3) an event engine for triggering, analysis, and debug. Incorporated inside an SoC, it enables rapid, automated analysis of supply impedance, as well as monitoring supply voltage droop of multi-core CPUs running full software workloads and during scan-test operations. To demonstrate these capabilities, we describe a power integrity case study of a dual-core ARM Cortex-A57 cluster in a commercial 28 nm mobile SoC. Measurements are presented of power delivery network (PDN) electrical parameters, along with waveforms of the CPU cluster running test cases and benchmarks on bare metal and Linux OS. The effect of aggressive power management techniques, such as power gating on the dominant resonant frequency and peak impedance, is highlighted. Finally, we present measurements of supply voltage noise during various scan-test operations, an often-neglected aspect of SoC power integrity.

KiloCore: A 32-nm 1000-Processor Computational Array

A processor array containing 1000 independent processors and 12 memory modules was fabricated in 32-nm partially depleted silicon on insulator CMOS. The programmable processors occupy 0.055 mm2 each, contain no algorithm-specific hardware, and operate up to an average maximum clock frequency of 1.78 GHz at 1.1 V. At 0.9 V, processors operating at an average of 1.24 GHz dissipate 17 mW while issuing one instruction per cycle. At 0.56 V, processors operating at an average of 115 MHz dissipate 0.61 mW while issuing one instruction per cycle, resulting in an energy consumption of 5.3 pJ/instruction. On-die communication is performed by complementary circuit and packet-based networks that yield a total array bisection bandwidth of 4.2 Tb/s. Independent memory modules handle data and instructions and operate up to an average maximum clock frequency of 1.77 GHz at 1.1 V. All processors, their packet routers, and the memory modules contain unconstrained clock oscillators within independent clock domains that adapt to large supply voltage noise. Compared with a variety of Intel i7s and Nvidia GPUs, the KiloCore at 1.1 V has geometric mean improvements of 4.3 $\times$ higher throughput per area and 9.4 $\times$ higher energy efficiency for AES encryption, 4095-b low-density parity-check decoding, 4096-point complex fast Fourier transform, and 100-B record sorting applications.

Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures

With ever-increasing on-chip current density, technology scaling is pushing the electromigration (EM)-induced robustness of silicon chips’ controlled collapse chip connection (C4) bump array to its limit. Since the density of C4 bumps is projected to be constant in the future, it is increasingly becoming challenging to guarantee EM-failure free for all power-supply bumps without increasing chip packaging cost or encroaching on bumps sites needed for I/O. In this paper, we develop a statistical simulation framework to analyze the mechanism and consequences of multiple power-bump wearout. Our analysis shows that the penalty of a moderate number of EM-induced power-bump failures is fairly small. A mild increase in on-chip supply voltage noise guardband can tolerate these bump failures and significantly increase a system mean-time-to-failure (MTTF). As a result, the targeted system MTTF can be achieved with significantly reduced power-bump count (e.g., 43% less) and a small extra noise margin (e.g., 0.5% $V_{\mathrm{ dd}}$ IR drop).

Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects

As technology shrinks, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise (PSN) plays a greater role in sub-100 nm technologies and creates signal integrity issues. It is vital to consider supply voltage noise effects: 1) during design validation to apply sufficient guardbands to critical paths, and 2) during path delay test to ensure the performance and reliability of the chip. In this paper, a novel layout-aware pattern generation procedure is proposed to maximize PSN effects on critical paths considering the impact of local voltage drop. The proposed pattern generation and validation flow is implemented on the ITC'99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented. Results demonstrate that our proposed method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed on the critical paths which results in increased path delay. The proposed method eliminates the very time consuming pattern validation phase that is practised in industry.

Power grid aware timing analysis using S-parameter

This article describes a novel technique for analysing the effects of supply voltage noise on circuit delay for VLSI circuits. Scattering parameters are used to model the supply voltage variation in the frequency domain and to reduce the original power grid and simulation time. The interconnections of the power grid are modelled by RLC passive elements, constant voltage and time-varying current sources. A fast and accurate MOSFET modelling method for a static timing analyser is proposed based on the power grid analysis. A MOSFET logic is modelled in three different regions during transition, and the maximum delay is formulated as a constrained non-linear optimisation problem by considering the power supply noise (inclusive of the IR-drop and the Ldi/dt drop). The proposed technique has been applied to ISCAS85 benchmark circuits redesigned in 45 nm technology. The results are compared to Hspice; they show that the error is within 5% of the Hspice simulation results.

A 1.25–5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS

A clock generator for high-speed chip-to-chip link receivers was implemented in a 45-nm CMOS SOI technology. A low sensitivity to supply voltage noise was achieved by means of a low dropout voltage regulator using a replica feedback in the regulation loop, where the replica resistance is regulated by a second loop. We show that by adjusting the replica load the necessary matching of the gm/gds ratio of the current sources can be achieved. A power supply rejection of > 22 dB was measured up to 1 GHz for a circuit operating from a 1 V supply with 80 pF decoupling capacitance and a load current of 18.5 mA. The maximum supply sensitivity of the clock generation circuit (DLL plus phase rotators) was 4.5 ps/100 mV supply noise over the entire noise frequency range at clock frequencies from 1.25-5 GHz. The phase rotator achieves a wide range of operating frequencies by providing programmable rise/fall times in its selection stage. In addition, low voltage operation of the circuit was demonstrated at supply voltages down to 0.7 V and a clock frequency of 1.6 GHz.

Intrinsic Noise and Temperature Coefficients of Selected Voltage References

We require voltage references with a relative output voltage noise of at most 10-6/radicHz in the frequency range of 0.1 mHz-1 Hz. We have investigated the output voltage noise and the external noise sources of a selection of references. Two external noise sources, i.e., supply voltage and temperature, and their coupling to the output voltage of the references were studied. The effect of supply voltage noise was negligible, whereas temperature noise had to be suppressed by stabilization. We found that samples of AD587LN- and MAX6126AASA50-type references fulfilled the requirements if the ambient temperature was stabilized to a level of approximately 50 mK/radicHz.

Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity

As chip integration continues to increase and technology scaling is forcing the operating voltage to decrease, modern designs have become more susceptible to supply voltage noise. However, even with a well designed power distribution network, modern at-speed test pattern generation techniques do not consider the maximum current throughput the network will be able to provide. As a result, conventional transition delay fault pattern generation tends to create a number of patterns that cause higher-than-average functional switching, which may cause timing and/or functional failures during test. In this paper, we propose a flow that incorporates the layout information and the locality of the switching activity during pattern generation to provide insight into the amount of tolerable switching. This will prevent both IR-drop related hot-spots and under-utilization of the chip since the switching activity can be evenly spread across the design. The results presented in this paper show significant improvement over our previous flow without negatively impacting fault coverage and pattern count.