Supply Pads Research Articles

An $S$ -Band GaAs Multifunction Chip for Transmit/Receive Modules

In this article, a highly integrated $S$ -band prototype multifunction chip (MFC) featuring high integration level, bidirectional operation, reduced number of pads, and optimized power consumption is demonstrated with a GaAs 0.15- $\mu \text{m}$ pHEMT technology. In order to pursue a high integration level, the MFC utilizes four amplifiers, two bidirectional mixers, and compact integrated passive filters. For the sake of power supply pads, the self-biasing technique is adopted with the on-chip power-combining technique. As for the power consumption minimization, when the system voltage is constant, the current reuse technique is selected with optimized transistor size without degradation of the key specifications. The main function for the MFC is to provide double-conversion and gain amplification both in the transmission path and the receiving path on one chip. In transmit mode, the MFC achieves 0-dB gain and 7-dBm $P_{-1\,\mathrm {dB}}$ from 2.6 to 3.2 GHz. The obtained local oscillator (LO)-radio frequency (RF) isolation is better than 50 dB, and the intermediate frequency (IF)-RF isolation is 85 dB. In receive mode, it achieves −5-dB gain with $V_{\mathrm {DD}}$ of the MFC is 5 V. The fabricated MFC occupied 5 mm $\times 5$ mm, which is the largest record area that the process can withstand.

A broadband GaAs pHEMT low noise driving amplifier with current reuse and self-biasing technique

A K/Ka-band two-stage low noise driving amplifier using a 0.15 μm GaAs pHEMT for low noise technology is designed and fabricated. In order to achieve broadband driving capability with low power consumption, current reuse technique is adopted to feed both transistors with the same DC power supply, which theoretically cuts the total current consumption in half. In addition, self-biasing technique is utilized to minimize both external power supply pads and chip footprint, which reduces the number of supply pads to a minimum of two (1 power pad and 1 ground pad). The circuit topology analysis and design procedures are also presented with an emphasis on noise figure and P1dB optimization. The low noise driving amplifier demonstrates a − 3 dB bandwidth of wider than 11 GHz, a power gain of 17 dB, an in-band mean noise figure of 2.2 dB and an in-band mean output P1dB of 6 dBm. The DC power consumption is 9.1 mA@3.3 V power supply. The chip size is 1 mm × 1.5 mm with only 1 external DC feed pad (3.3 V) and 1 ground pad (0 V). With the performance comparable to typical two-stage dual-bias low noise driving amplifier counterparts, the proposed MMIC is more attractive to chip/system users in volume-limited and power-contrained applications.

A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems

We propose in this paper a novel configurable multi-power-rail pad that combines power supply support circuits and a digital input/output (I/O) buffers designed for a wafer-scale system. This wafer-scale platform includes a reconfigurable wafer-scale circuit, the WaferIC, comprising an alignment-insensitive surface that can be configured to interconnect any digital components manually deposited on its surface. The proposed multi-power-rail pad minimizes power losses and heat dissipation within the circuit. The pad that is fed from two distinct voltage sources providing power at 1.8 and 3.3 V has been implemented and tested. This pad has two merged configurable control loops that can select the power source. Merging takes place through shared transistors. This dual supply pad embeds a voltage regulator that achieves a fast response time of 21.1 ns and that can operate over a wide range of configurable regulated output voltage, from 500 mV up to 2.955 V. This regulator is capable of providing a maximum output current of 40 mA while needing only a very small quiescent current of 126 μA. The regulator's power supply noise rejection ranges from -25 down to -40 dB for frequencies ranging from 1 kHz up to 1 MHz. The embedded digital I/O pad shares a common output with the power distribution and can be configured from 0.5 up to 3.3 V for a maximum speed of 250 MHz.

IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption

A compact IR-drop model for on-chip power distribution networks in array and wire-bonded ICs is analyzed. Chip dimensions, size, and location of the supply pads, metal coverage, piecewise distribution of IC consumption, and the resistance between the pads and the power supply are considered to obtain closed-form expressions for the IR-drop. The IR-drop model is validated by comparing its results with electrical simulations. The obtained error is in the range of 1%.

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

Power Supply Pads Assignment for Maximum Timing Yield

The design of power distribution networks significantly impacts the timing of very large scale integrated chips. Process variations induce uncertainty in the current drawn off the network and, therefore, impose statistical measures on the supply voltage. This brief presents an optimization methodology for assigning power supply pads across the chip for maximizing the timing yield. A mixed-integer nonlinear programming optimization problem subject to the voltage drop and current constraints is efficiently solved to find the optimum number and location of the pads. The experimental results for ISCAS89 benchmark circuits demonstrate as much as a 30% improvement in the timing yield.

A Low Power V-Band Injection-Locked Frequency Divider in 0.13-.MU.m Si RFCMOS Technology

In this work, a divide-by-2 injection locked frequency divider (ILFD) operating in the V-band with a low DC power consumption has been developed in a commercial 0.13-µm Si RFCMOS technology. The bias current path was separated from the injection signal path, which enabled a small supply voltage of 0.5V, leading to a DC power consumption of only 0.31mW. To the authors' best knowledge, this is the lowest power consumption reported for mm-wave ILFDs at the point of writing. All inductors and interconnection lines were designed based on EM (electromagnetic) simulator for precise prediction of circuit performance. With varactor tuning voltage ranged for 0-1.2V, the free-running oscillation frequency varied from 27.43 to 28.06GHz. At 0dBm input power, the frequency divider exhibited a locking range of 5.8GHz from 53 to 58.8GHz without external tuning mechanism. The fabricated circuit size is 0.72mm × 0.62mm including the RF and DC supply pads.

Successive Pad Assignment for Minimizing Supply Voltage Drop

An efficient pad assignment methodology to minimize voltage drop on a power distribution network is proposed. A combination of successive pad assignment (SPA) with incremental matrix inversion (IMI) determines both location and number of power supply pads to satisfy drop voltage constraint. The SPA creates an equivalent resistance matrix which preserves both pad candidates and power consumption points as external ports so that topological modification due to connection or disconnection between voltage sources and candidate pads is consistently represented. By reusing sub-matrices of the equivalent matrix, the SPA greedily searches the next pad location that minimizes the worst drop voltage. Each time a candidate pad is added, the IMI reduces computational complexity significantly. Experimental results including a 400 pad problem show that the proposed procedures efficiently enumerate pad order in a practical time.

Defect Detection Using Quiescent Signal Analysis

IDDQ or steady state current testing has been extensively used in the industry as a mainstream defect detection and reliability screen. The background leakage current has increased significantly with the advent of ultra deep submicron technologies. This increased background leakage noise makes it difficult to differentiate defect-free devices from those with defects that draw significantly small amount of currents. Therefore it is impossible to use single threshold IDDQ testing for today’s technologies. Several techniques that improve the resolution of IDDQ testing have been proposed to replace the single threshold detection scheme. However, even these techniques are suffering from loss of resolution that is required for detection of subtle defects in the presence of leakage currents in excess of a few mA. All these techniques use a single IDDQ measurement for detection and thus the scalability of these techniques is limited. Quiescent Signal Analysis (QSA) is a novel IDDQ defect detection and diagnosis technique that uses IDDQ measurements at multiple chip supply pads. Implicit in our methodology is a leakage calibration technique that scales the total leakage current over multiple simultaneous measurements. This helps in decreasing the background leakage component in individual measurements and thus increases the resolution of this technique to subtle defects. Defect detection is accomplished by applying linear regression analysis to the multiple supply port measurements and using outlier analysis to identify defective devices. The effectiveness of this technique is demonstrated in this paper using simulation experiments on portion of a production power grid. Predicted chip size and leakage values from the International Technology Roadmap for semiconductors (ITRS) are used in these experiments. One of the other major concerns expressed in ITRS is that of significant increase in intra-die process variations. The performance of the proposed technique in presence of such variations is evaluated using three different intra-die process variation distribution models.

Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids

Quiescent Signal Analysis (QSA) is a novel electrical-test-based diagnostic technique that uses IDDQ measurements made at multiple chip supply pads as a means of locating shorting defects in the layout. The use of multiple supply pads reduces the adverse effects of leakage current by scaling the total leakage current over multiple measurements. In previous work, a resistance model for QSA was developed and demonstrated on a small circuit. In this paper, the weaknesses of the original QSA model are identified, in the context of a production power grid (PPG) and probe card model, and a new model is described. The new QSA algorithm is developed from the analysis of IDDQ contour plots. A “family” of hyperbola curves is shown to be a good fit to the contour curves. The parameters to the hyperbola equations are derived with the help of inserted calibration transistors. Simulation experiments are used to demonstrate the prediction accuracy of the method on a PPG.

A 250-Mb/s 32*32 CMOS crosspoint LSI for ATM switching systems

In the CMOS cross-point LSI described, fully synchronous switching capability for fixed-length ATM cells (packets), as well as the functions of conventional cross-point switches, has been realized. Packet broadcast capability has also been achieved as the result of input-oriented bit-map routing architecture. In order to exchange 32 packet links at the broadband line speed, tristate buffers and control latches with reduced parasitic capacitors have been utilized. The 40 k transistor chip is fabricated with a 1.0- mu m double-metal-layer n-well CMOS technology. The switch matrix is 2.4*3.2 mm. The chip size, 7.4*7.4 mm, is set by the 113 signal pads and the 39 voltage supply pads. Voltage supply nodes for output buffers are completely separated from the others. 250-Mb/s operation has been verified under nominal conditions with a 176-pin PGA package. Operating from a -4.5-V supply at 160 Mb/s, the chip dissipates 1.2 W. >