Superscalar Research Articles

Memory Dependence Speculation for Simultaneous Multi-Threading Processors

Simultaneous Multi-Threading (SMT) processors provide improvement over the traditional out-of-order superscalar architecture by allowing instructions from several independent threads to execute out-of-order concurrently. Maintaining the accuracy of values read from and written to memory is a great bottleneck for processor performance, as loads must stall execution until all prior store addresses are known or risk reading invalid data. Prior research in this area has mainly focused on superscalar architecture, as such, it is only natural to extend memory dependence speculation techniques to an SMT architecture. In this paper, we allow for loads among threads to execute as soon as their addresses are resolved without checking for prior memory address conflicts. Stores also perform a check on all later loads to see if any read was too early due to an address match, if so, the processor state is recovered, and the load re-issued. This aggressive technique allows for the greatest potential instructions per clock cycle gains over predictive techniques as the pipeline is never stalled for loads. Our simulations show that an overall IPC gain up to 12% and 10% is possible for both 4-threaded and 8-threaded workloads respectively. Conversely, a maximum overall IPC loss of at least 2.3% and 2% for 4-threaded and 8-threaded workloads respectively was also observed.

A flexible soft error mitigation framework leveraging dynamic partial reconfiguration technology

Fault tolerance is crucial for mission-critical FPGA-based systems in radiation environments. Soft-core processors in these systems, performing both control and computational tasks, require efficient soft error mitigation techniques to enhance their fault tolerance. In this paper, we investigate the variation trends in the fault tolerance of various processor components as the software workload changes. Based on our investigation, we propose a reconfigurable soft error mitigation framework that dynamically switches the hardening strategies for the processor according to the running workloads. The innovative application of dynamic partial reconfiguration technique in FPGAs enables time-multiplexing of the same circuit region to accommodate various hardening schemes, consequently achieving high area efficiency. We apply the framework to an open-source dual-issue superscalar RISC-V processor on a Xilinx ZCU102 FPGA board. Compared to traditional spatial redundancy-based hardening techniques, the proposed framework achieves a 20.84 % reduction in LUT utilization and a 20.53 % reduction in flip-flop utilization. The effectiveness of our framework has been evaluated through fault injection campaigns. The results indicate that, on average, only 0.05 % of faults would lead to system failure after hardening. Therefore, our work offers a new perspective on dynamic soft error mitigation in reconfigurable systems.

A promising approach using Fibonacci sequence-based optimization algorithms and advanced computing

In this paper, the feasibility of Structural Health Monitoring (SHM) employing a novel Fibonacy Sequence (FS)-based Optimization Algorithms (OAs) and up-to-date computing techniques is investigated for a large-scale railway bridge. During recent decades, numerous metaheuristic intelligent OAs have been proposed and immediately gained a lot of momentum. However, the major concern is how to employ OAs to deal with real-world problems, especially the SHM of large-scale structures. In addition to the requirement of high accuracy, a high computational cost is putting up a major barrier to the real application of OAs. Therefore, this article aims at addressing these two aforementioned issues. First, we propose employing the optimal ability of the golden ratio formulated by the well-known FS to remedy the shortcomings and improve the accuracy of OAs, specifically, a recently proposed new algorithm, namely Salp Swarm Algorithm (SSA). On the other hand, to deal with the high computational cost problems of OAs, we propose employing an up-to-date computing technique, termed superscalar processor to conduct a series of iterations in parallel. Moreover, in this work, the vectorization technique is also applied to reduce the size of the data. The obtained results show that the proposed approach is highly potential to apply for SHM of real large-scale structures.

Specially-Designed Out-of-Order Processor Architecture for Microcontrollers

In very large-scale integration circuit (VLSI) systems, microcontrollers are often implanted to manage the whole system to complete the given computing tasks. They play an essential part as regulators, which should allocate resources steadily and issue instructions promptly to drive functional units. However, most of the recent research focuses on the operation at the software level or the scheduling at the SoC level, ignoring the impact of the microarchitecture and the features of controlled sub-modules. This paper analyzes the requirements of microcontrollers in the VLSI system with various constraints and conditions that should be considered in the hardware implementation of such microarchitecture. Furthermore, this paper takes an open-source design using RISC-V ISA as the prototype to implement hardware microarchitecture. This design integrates the techniques of out-of-order processing, which are usually used on superscalar processors. As a result, the design quadruples the number of pipelined instructions, greatly alleviating the stalling of the instruction stream with a maximum extra look up table utilization of 18.37% in FPGA implementation.

HAIR: Halving the Area of the Integer Register File with Odd/Even Banking

This article proposes a new microarchitectural scheme for reducing the hardware complexity of the integer register file of a superscalar processor. The register file is split into two banks holding even-numbered and odd-numbered physical registers, respectively. Each bank provides one read port to each two-input integer execution unit. This way, each bank has half the total number of read ports, and the register file area is roughly halved, which reduces the energy dissipated per register access and the register access time. However, a bank conflict occurs when both inputs of a two-input micro-operation lie in the same bank. Bank conflicts hurt performance, and we propose a simple solution to remove most bank conflicts, thus recovering most of the lost performance.

Towards the Improvement of Branch Instructions Identification in High- Performance Processors: Issues, Challenges and Techniques

Introduction: Accurate branch prediction technique has become compulsory in the superscalar and deep pipeline processors. The conditional instructions can break the continuous flow of execution in the pipeline stages, thereby decreasing processor performance. Discussion: This paper highlights the concept of branch prediction, some issues and challenges, and techniques for improving processor performance. Further, this paper also presents the role of branch prediction in different processors and their features. Conclusion: The concept of the branch prediction used in parallel processors to enhance the execution speed of the conditional branch instructions and improve the processor's performance is highlighted in this paper. Further, this paper highlights the branch predictor techniques with their features and presents the challenges, issues, and future techniques related to the branch prediction.

Design of a 32-Bit, Dual Pipeline Superscalar RISC-V Processor on FPGA: A Review

Abstract: A 40 MHz with 32-bit and 5-stage dual-pipeline superscalar processor based on RISC-V Instruction Set Architecture is presented. It supports integer, multiply-divide and atomic read-modify-write operations. The proposed system implements inorder issuing of instructions. The design includes a dynamic branch prediction unit, memory subsystem with virtual memory, separate instruction cache and data cache, integer and floating-point execution units, interrupt controller, error control module, and a UART peripheral. Individual interrupts can have up to four levels of primary priority set in the interrupt controller. For the main memory, the error control module provides single error correction and double error detection. For on-chip communication, the Wishbone B.3 bus standard is used. On a Virtex-7 XC7VX485T FFG 1761-2 FPGA-based board, the processor is implemented. The architecture has CoreMark and Dhrystone benchmark ratings of 3.84/MHz and 1.0603 DMIPS/MHz, respectively

Formal modeling and verification for amplification timing anomalies in the superscalar TriCore architecture

Formal modeling and verification for amplification timing anomalies in the superscalar TriCore architecture

A Comprehensive Method for Liquid-to-Solid Interactions.

Realistic real-time water-solid interaction has been an open problem in Computer Graphics since its beginnings, mainly due to the complex interactions that happen at the interface between solid objects and liquids, both when objects are completely or partially wet, or when they are fully submerged.In this paper we present a method that tackles the two main aspects of this problem, namely the buoyancy of objects submerged into fluids, and the superficial liquid propagation and appearance changes that arises at the interface between the surface of solid objects in contact with a liquids.For the first problem (buoyancy) a method is proposed to realistically compute the fluid-to-solid coupling problem. Our proposal is suitable for a wide spectrum of cases, such as rigid or deformable objects, hollow or filled, permeable or impermeable, and with variable mass distribution. In the case of permeable materials, which allow liquid to pass through the object, the presented method incorporates the dynamics of the fluid in which the object is submerged, and decouples the computation of the physical quantities involved in the buoyancy force of the empty object with respect to to the liquid contained within it. On the other hand, the visual appearance of certain materials depends on their intrinsic light transfer properties, the lighting present and other environmental contributions. Thus, complementing the first approach in this paper, a new technique is introduced to model and render the appearance changes of absorbent materials when there is liquid on their surface. Also, a new method was developed to solve the problem of the interaction between the object surface and liquids, taking advantage of texture coordinates. An algorithm was proposed to model the main physical processes that occur on the surface of a wet or wet solid object. Finally, we model the change in appearance that typically arise in most materials in contact with fluids, and an algorithm is implemented achieving real-time performance. The complete solution is designed taking advantage of superscalar architectures and GPU acceleration, allowing a flexible integration with the pipelines of current graphic engines.

Engineering In-place (Shared-memory) Sorting Algorithms

We present new sequential and parallel sorting algorithms that now represent the fastest known techniques for a wide range of input sizes, input distributions, data types, and machines. Somewhat surprisingly, part of the speed advantage is due to the additional feature of the algorithms to work in-place, i.e., they do not need a significant amount of space beyond the input array. Previously, the in-place feature often implied performance penalties. Our main algorithmic contribution is a blockwise approach to in-place data distribution that is provably cache-efficient. We also parallelize this approach taking dynamic load balancing and memory locality into account. Our new comparison-based algorithm In-place Parallel Super Scalar Samplesort ( IPS 4 o ) , combines this technique with branchless decision trees. By taking cases with many equal elements into account and by adapting the distribution degree dynamically, we obtain a highly robust algorithm that outperforms the best previous in-place parallel comparison-based sorting algorithms by almost a factor of three. That algorithm also outperforms the best comparison-based competitors regardless of whether we consider in-place or not in-place, parallel or sequential settings. Another surprising result is that IPS 4 o even outperforms the best (in-place or not in-place) integer sorting algorithms in a wide range of situations. In many of the remaining cases (often involving near-uniform input distributions, small keys, or a sequential setting), our new In-place Parallel Super Scalar Radix Sort ( IPS 2 Ra ) turns out to be the best algorithm. Claims to have the – in some sense – “best” sorting algorithm can be found in many papers which cannot all be true. Therefore, we base our conclusions on an extensive experimental study involving a large part of the cross product of 21 state-of-the-art sorting codes, 6 data types, 10 input distributions, 4 machines, 4 memory allocation strategies, and input sizes varying over 7 orders of magnitude. This confirms the claims made about the robust performance of our algorithms while revealing major performance problems in many competitors outside the concrete set of measurements reported in the associated publications. This is particularly true for integer sorting algorithms giving one reason to prefer comparison-based algorithms for robust general-purpose sorting.

A Refinement-Based Approach to Spectre Invulnerability Verification

Several mitigations to thwart Spectre attacks have been proposed. However, design errors or trojans can be exploited to circumvent these mitigations. We have developed a highly-automated formal verification methodology that can detect if modern microprocessor designs are vulnerable to Spectre and its variants or prove otherwise. The methodology comprises of a refinement-based formal Spectre invulnerability property, and refinement maps, abstractions and invariants required to efficiently check the property. The methodology was evaluated on 29 benchmarks based on the RSD, which is an open source RISC-V based out-of-order superscalar processor. The benchmarks incorporated two Spectre defenses including software-controlled speculation and data track. Also incorporated were various implementation errors and hardware Trojans such as internally-triggered, rare-circuit-state and time-bombs that induce Spectre. What was evaluated was if the methodology could efficiently prove that an implementation is not vulnerable to Spectre and provide a counterexample otherwise. The methodology provided accurate classification for all benchmarks. The verification times were very efficient, ranging from 30 seconds to 1,500 seconds.

Combining the Forwarding with Delay Slots Operations to Avoid the Branch Misprediction Penalty in Superscalar Processors

Using pipeline system in modern possessors has contributed significantly to the development of processors performance by increasing its speed faster than before, where CPI approaches to 1, however, this technique accompanied many problems, one of them called Branch Misprediction penalty due to control hazard, most of them occurs when implementing dynamic branch prediction. For every five jump commands of a program there is jump command, which causes interruption of the execution of orders through pipeline systems. There are many proposed previews studies, such as Dynamic Branch Prediction and Control Speculation, NTB Branch Predictor: Dynamic Branch Predictor for High-Performance Embedded Processors. This paper presents a new mechanism to combine forwarding and delay slots together to avoid a Branch Misprediction Penalty in Superscalar Processors, it's got better results

Design of Low Power Cam Memory Cell for the Next Generation Network Processors

In the modern world, high performance embedded applications in the field of multimedia, networking, and imaging are increasing day by day. These applications require high performance and more complex out-of-order superscalar processor. These complex dynamic instructions scheduling superscalar processors need higher levels of on-chip integration designs which are often associated with power dissipation. These out-of-order superscalar processors achieve higher performance compared to other processors by simultaneous fetching, decoding and execution for multiple instructions in out-of-order that are used in the next generation network processors. The main data path resources of the processor use CAM+RAM structure which is the major power consuming unit in the overall out-of-order processor design. The proposed new design of CAM+RAM with power-gating technique reduces the overall average power consumption compared to the conventional design without any significant impact on their performance.

Scrambled Linear Pseudorandom Number Generators

F 2 -linear pseudorandom number generators are very popular due to their high speed, to the ease with which generators with a sizable state space can be created, and to their provable theoretical properties. However, they suffer from linear artifacts that show as failures in linearity-related statistical tests such as the binary-rank and the linear-complexity test. In this article, we give two new contributions. First, we introduce two new F 2 -linear transformations that have been handcrafted to have good statistical properties and at the same time to be programmable very efficiently on superscalar processors, or even directly in hardware. Then, we describe some scramblers , that is, nonlinear functions applied to the state array that reduce or delete the linear artifacts, and propose combinations of linear transformations and scramblers that give extremely fast pseudorandom number generators of high quality. A novelty in our approach is that we use ideas from the theory of filtered linear-feedback shift registers to prove some properties of our scramblers, rather than relying purely on heuristics. In the end, we provide simple, extremely fast generators that use a few hundred bits of memory, have provable properties, and pass strong statistical tests.

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that no hardware-accelerated string sorters have been proposed yet. In this paper, we present Parallel Hybrid Super Scalar String Sample Sort (pHS5) on Intel HARPv2, a heterogeneous CPU-FPGA system with a server-grade CPU. Our pHS5 extends pS5, the state-of-the-art string sorting algorithm for multi-core shared memory CPUs, by adding multiple processing elements (PEs) on the FPGA. Each PE accelerates one instance of the most effectively parallelizable among the dominant kernels of pS5 by up to 33% compared to a single Intel Xeon Broadwell core despite a clock frequency that is 17 times slower. Furthermore, we extended the job scheduling mechanism of pS5 to schedule the accelerable kernel not only among available CPU cores but also on our PEs, while retaining the complex high-level control flow and the sorting of the smaller data sets on the CPU. Overall, we accelerate the entire algorithm by up to 10% with respect to the 28-thread software baseline running on the Xeon processor and by up to 36% at lower thread counts. Finally, we generalize our results assuming pS5 as representative of software that is heavily optimized for modern multi-core CPUs and investigate the performance and energy advantage that an FPGA in a datacenter setting can offer to regular RTL users compared to additional CPU cores.

Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design

Soft Error Rate (SER) estimation is an important challenge for integrated circuits because of the increased vulnerability brought by technology scaling. This paper presents a methodology to estimate in early stages of the design the susceptibility of combinational circuits to particle strikes. In the core of the framework lies MASkIt , a novel approach that combines signal probabilities with technology characterization to swiftly compute the logical, electrical, and timing masking effects of the circuit under study taking into account all input combinations and pulse widths at once. Signal probabilities are estimated applying a new hybrid approach that integrates heuristics along with selective simulation of reconvergent subnetworks. The experimental results validate our proposed technique, showing a speedup of two orders of magnitude in comparison with traditional fault injection estimation with an average estimation error of 5 percent. Finally, we analyze the vulnerability of the Decoder, Scheduler, ALU, and FPU of an out-of-order, superscalar processor design.

Evaluation and Proposal of a Lightweight Reconfigurable Accelerator for Heterogeneous Multicore

Nowadays, with the spread of mobile devices, energy efficiency and performance have become important requirements in system design. These devices need enough performance to run increasingly complex applications at the lowest possible energy cost to extend battery life. Heterogeneous systems have proven to be a promising solution to meet such demands. Generally, such systems consist of cores that offer either energy efficiency or high performance. This work proposes a reconfigurable accelerator, called ALLEGRI, and evaluates its impact on performance and energy consumption considering three different versions of a multicore processor, varying the superscalar processor issue width (single, dual and four issue). The parmibench suite was used to evaluate the system. The results show that the version that has the best energy efficiency and the best performance was the single-issue multicore + ALLEGRI and four-issue + ALLEGRI, respectively.

Dynamic issue queue capping for simultaneous multithreaded processors

A simultaneous multithreaded (SMT) processor mixes multiple instruction streams in its superscalar out-of-order execution core for higher throughput. To achieve this, a superscalar processor is modified in such a way that someof its resources are duplicated and the rest is shared among multiple threads. The issue queue (IQ), which holds allwaiting instructions until they become ready and scheduled for execution, is among these shared resources. A baselineunmanaged IQ can give an unexpectedly low performance since a hungry thread can tie up most of the IQ entries.This type of scenario is also worse in terms of the fairness metric since some of the threads may experience starvation.Earlier studies propose both static and a limited type of dynamic capping of the IQ entries for regulating IQ traffic andproviding better SMT throughput and fairness. In this study, we propose an e?iciency-based dynamic capping (EDC)algorithm that calculates an efficiency metric for each thread and allocates the IQ entries for maximizing the throughputand the fairness metrics. EDC gives 3.6% better throughput and 3.9% better fairness results compared to the currentstate-of-the-art algorithms, on the average.

Microarchitectural Characterization on a Mobile Workload

Geekbench is one of the most referenced cross-platform benchmarks in the mobile world. Most of its workloads are synthetic but some of them aim to simulate real-world behavior. In the mobile world, its microarchitectural behavior has been reported rarely since the hardware profiling features are limited to the public. As a popular mobile performance workload, it is hard to find Geekbench’s microarchitecture characteristics in mobile devices. In this paper, a thorough experimental study of Geekbench performance characterization is reported with detailed performance metrics. This study also identifies mobile system on chip (SoC) microarchitecture impacts, such as the cache subsystem, instruction-level parallelism, and branch performance. After the study, we could understand the bottleneck of workloads, especially in the cache sub-system. This means that the change of data set size directly impacts performance score significantly in some systems and will ruin the fairness of the CPU benchmark. In the experiment, Samsung’s Exynos9820-based platform was used as the tested device with Android Native Development Kit (NDK) built binaries. The Exynos9820 is a superscalar processor capable of dual issuing some instructions. To help performance analysis, we enable the capability to collect performance events with performance monitoring unit (PMU) registers. The PMU is a set of hardware performance counters which are built into microprocessors to store the counts of hardware-related activities. Throughout the experiment, functional and microarchitectural performance profiles were fully studied. This paper describes the details of the mobile performance studies above. In our experiment, the ARM DS5 tool was used for collecting runtime PMU profiles including OS-level performance data. After the comparative study is completed, users will understand more about the mobile architecture behavior, and this will help to evaluate which benchmark is preferable for fair performance comparison.

Exploring Cortex-M Microarchitectural Side Channel Information Leakage

The growing Internet of Things (IoT) market demands side-channel attack resistant, efficient, cryptographic implementations. Such implementations, however, are microarchitecture-specific, and cannot be implemented without an in-depth structural knowledge of the CPU and memory information leakage patterns; a description of such information leakages is presently not disclosed by any processor design company. In this work we propose the first Instruction Set Architecture (ISA) level framework for microarchitectural leakage characterization. Our framework allows to extract a microarchitectural leakage profile from any superscalar in-order processor; we infer detailed pipeline characteristics through the observation of instruction timings, and provide an identification of the datapath registers via a side-channel measuring setup. The extracted model can serve as a foundation for building solid countermeasures against side-channel attacks on software cryptographic implementations. We validate the extracted models on the ARM Cortex-M4 and ARM Cortex-M7 CPUs, the latter being the most powerful CPU of the ARM microcontrollers offer. Finally, as a further demonstration of our model’s accuracy, we mount a successful attack on unprotected AES implementations for each of the examined platforms.