Superjunction Lateral Double-diffused MOSFET Research Articles

Super Junction Lateral Double-Diffused MOSFET with Ultra-low Specific on-Resistance Completely Eliminating Substrate Assisted Depletion Effect

Super Junction Lateral Double-Diffused MOSFET with Ultra-low Specific on-Resistance Completely Eliminating Substrate Assisted Depletion Effect

A novel LDMOS with optimized electric field distribution to eliminate substrate assisted depletion effect

A novel N-channel Super Junction Lateral double-diffused MOSFET (SJ LDMOS) with optimized electric field distribution is proposed. To eliminate substrate assisted depletion (SAD) effect, the source-drain electrodes of the proposed device are used to form a voltage in the substrate equal to the SJ layer. Then the surface of the substrate is depleted through the buffer layer. The substrate and the SJ layer are independently depleted, and form a similar electric field distribution. The influence of the substrate on the SJ layer is greatly removed. Finally, the influence of the substrate on SJ layer is completely eliminated. Under the same drift length of 20 μm, the specific on resistance (Ron,sp) and breakdown voltage (BV) of the proposed SJ LDMOS are reduced by 60.09% and 28.9% compared with those of the conventional SJ LDMOS, respectively. With the increase of the drift region length, the SJ LDMOS which eliminates the SAD effect has more obvious advantages in the high voltage field.

Novel Superjunction LDMOS With a High-K Dielectric Trench by TCAD Simulation Study

A novel superjunction (SJ) lateral double-diffused MOSFET (LDMOS) with a deep High-K(HK) dielectric trench (HK SJ-LDMOS) is proposed and its mechanism is investigated by Technology Computer Aided Design (TCAD) simulations. The HK dielectric trench is embedded under the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> drain, which is connected with the drain electrode. In the OFF-state, the reshaping effect of HK trench enhances the bulk electric field strength and weakens the peak electric field around the edge of the drain diffusion, which increases the breakdown voltage (BV). Moreover, because of the assistant depletion effect by the HK trench, a lower resistivity substrate is allowed for HK SJ-LDMOS, which also increases the doping concentration of the ntype buffer layer under the SJ layer of HK SJ-LDMOS, correspondingly. Thus, a lower specific ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> ) is also obtained. Simulation results show that the BV increases by 35.2% in comparison with the conventional buffered SJ-LDMOS with the same drift length. Moreover, HK SJ-LDMOS presents an excellent figure of merit, which is two times higher than that of the conventional buffered SJ-LDMOS.

Super junction LDMOS with P-trench and stepped buried oxide layer for high performance

In this paper, a new silicon-on-insulator superjunction lateral double-diffused MOSFET (SOI SJLDMOS) with a p-trench layer and stepped buried oxide, is investigated using 3D numerical simulation. The p-trench layer and stepped buried oxide distinguish it from a conventional SOI SJLDMOS. The etched buried oxide layer, with its stepped buried -oxide structure, which facilitates a more even electric field distribution via the electric field modulation effect, increases the breakdown-voltage (BV). Furthermore, the p-trench layer improves the doping concentration through compensation depletion, which further decreases the specific on-resistance (Ron,sp). The simulation indicates that the new device has a higher BV (increased by 29%) than the conventional SOI SJLDMOS. At the same time, Ron,sp decreases by 20% for the on-state for a given drift-region length.

New superjuction LDMOS with surface and bulk electric field modulation by buffered step doping and multi floating buried layers

A new superjunction lateral double diffused MOSFET with surface and bulk electric field modulation (SBEFM SJ-LDMOS) by applying of multiple floating buried layers and buffered step doping is proposed in this paper. The Multiple N-type floating buried layers are embedded in P-substrate, to reduce the amount of field crowding at N+/N-buffer/P-substrate junction by spreading the vertical depletion layer, which effectively improves the bulk electric field distribution in SJ-LDMOS, and the N+/N-buffer/P-substrate junction and the auxiliary MFB layers/substrate junctions jointly sustain a high vertical breakdown voltage (BV). In addition, based on the buffered step doping layer under the SJ layer, a uniform lateral electric field at the drift region surface of the device is obtained. Therefore, the bulk and surface electric field are both optimized simultaneously in SBEFM SJ-LDMOS. Simulated results show that compared with the conventional Buffered SJ-LDMOS and BSD SJ-LDMOS, the proposed SBEFM SJ-LDMOS improves BV by 131.7% and 80.4%, respectively, at the same drift region length and with low specific ON-resistance (RON,sp). SBEFM SJ-LDMOS exhibits excellent performance with the power figure-of-merit (FOM=BV2/RON,sp) of 13.07 MW/cm2.

Trench-gate-integrated superjunction lateral double-diffused MOSFET with low specific on-resistance

In this paper, a new low-voltage planar gate superjunction (SJ) lateral double-diffused MOSFET (LDMOSFET) is presented. The proposed trench-gate-integrated SJ-LDMOSFET is composed of a conventional planar gate structure and a trench gate structure extending into a drift region through a channel region, which helps reduce both drift resistance and channel resistance. By device simulation, we confirmed that current crowding near the top surface was alleviated by the spread of electron current into the drift region through the accumulation layer of the trench gate. As a result, the specific on-resistance (RON · A) of the trench-gate-integrated SJ-LDMOSFET can be reduced by increasing SJ thickness (TSJ), and the trench-gate-integrated SJ-LDMOSFET with a TSJ of 4 µm achieved an RON · A of 0.47 mΩ·cm2 at a breakdown voltage of 97 V. This is about 14% lower than the one-dimensional Si limit.

A New Solution for Superjunction Lateral Double Diffused MOSFET by Using Deep Drain Diffusion and Field Plates

A new solution based on the concept of a deep drain diffusion combined with field plates (FPs) is proposed for the superjunction lateral double diffused MOSFET (SJ-LDMOS) device. The deep drain diffusion suppresses the curvature effect of the conventional SJ-LDMOS and the FPs optimize the electric field distribution further. Simulated results show that the proposed SJ-LDMOS exhibits figure of merits of 12.8 and 8.5 MW/cm $^{\mathrm{{2}}}$ for 700 and 1200 V ratings, respectively, which are about 20% better than the prior art. Moreover, the proposed SJ-LDMOS is less sensitive to the charge imbalance. Using the isotropic etch technique followed by implantation, the deep drain diffusion is easy to be fabricated.

A novel substrate termination technology for lateral double-diffused MOSFET based on curved junction extension

In this paper, a novel substrate termination technology (STT) for lateral double-diffused MOSFET (LDMOS) based on curved junction extension is proposed and experimentally demonstrated. A low-doped P-substrate, which is inserted in the curved region of the LDMOS, adjusts the high-doped abrupt P-body/N-drift junction with small curvature radius to low-doped P-sub/N-drift junction with large curvature radius, thus reducing peak electric field and avoiding premature avalanche breakdown at the curved abrupt P-body/N-drift junction. The proposed STT has been applied to a super junction (SJ) LDMOS. The experimental results show that the SJ LDMOS with the proposed STT exhibits off-state breakdown voltage (BV) of 800 V, which is the highest BV for the reported SJ LDMOS by far.

New super junction lateral double-diffused MOSFET with electric field modulation by differently doping the buffered layer

In order to break through the limit relationship between the breakdown voltage and specific on-resistance for LDMOS (lateral double-diffused MOSFET), a new super junction LDMOS is proposed with the electric field modulation by differently doping the buffered layer in this paper for the first time based on the buffered SJ-LDMOS. The new electric field introduced by the differently doping buffered layer, owing to the electric field modulation, is brought to the surface electric field of SJ-LDMOS, which alleviates a low lateral breakdown voltage due to the uneven electric field distribution for the LDMOS affected by the vertical electric field. Through the ISE simulation, the results are obtained that the surface electric field is optimized for the proposed SJ-LDMOS when the number of differently doping buffered layers is three. The saturated breakdown voltage for the new SJ-LDMOS is increased by about 50% compared with that for conventional LDMOS, and improved by about 32% compared with that for buffered SJ-LDMOS. The lateral breakdown voltage for unit length is increased to 18.48 V/μm. For the proposed SJ-LDMOS, the specific on-resistance is 25.6 mΩ· cm2 with a breakdown voltage of 382 V, which already breaks the limit relationship of 71.8 mΩ·cm2 with a breakdown voltage of 254 V in the conventional LDMOS.

Suppress of Substrate-Assisted Depletion Effects in Super Junction LDMOS on Thin Film SOI

Conventional super-junction lateral double diffused MOSFET (SJ-LDMOS) fabricated on Silicon on Insulator (SOI) substrate suffers from low breakdown voltage under the same on-resistance due to substrate-assisted depletion effect. To suppress this effect, it is important to find the charge density in the inversion layer under buried oxide. In this paper, we propose a charge density equation and its formulation. The results were used in a 3D device simulator to optimize the device structure. The experimental results confirm that the equation is useful to optimize device performance. The breakdown voltage of structure increased 54% and on-state-resistance decreased 58% compared to conventional SJ device. The device fabrication procedure is fully compatible with mainstream SOI CMOS process.

A Review of Super Junction LDMOS

Super Junction Lateral Double-diffused MOSFET (SJ-LDMOS) is one of the important attractive devices in high-voltage integrated circuit and power integrated circuit. However, the SJ-LDMOS is generally implemented on a low-resistance substrate, which always suffers from substrate-assisted depletion (SAD) effect, which thus degrades the performance of devices. A number of literatures have been published to solve the SAD effect and improve performance. This review summarizes the developments made in SJ-LDMOS based on bulk silicon, silicon on insulator, and silicon on sapphire in the last 10 years. Finally, the future work what researchers can do on the SJ-LDMOS also has been proposed.

New Superjunction LDMOS With $N$-Type Charges' Compensation Layer

A new superjunction lateral double diffused MOSFET (LDMOST) is designed with an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -type buried layer in the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> -substrate near the drain to suppress the effect of substrate-assisted depletion resulting from <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -type charges' compensating charges' imbalance between the pillars of the superjunction layer. By the effect of the electric field modulation, a more uniform surface electric field is obtained by the new high electric field peak introduced by the p-n junction of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> -substrate and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -type charges' compensation layer. The new effect of reduced bulk field is introduced to improve the vertical breakdown voltage (BV) by reducing the high bulk electric field around the drain. Fabricated <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -buried SJ LDMOST with a drift region length of 35 mum and a pillar width of 4.0 mum exhibits a specific on resistance of 98 mOmegamiddotcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a BV of 410 V.

New CMOS compatible super-junction LDMOST with n-type buried layer

A new super-junction lateral double diffused MOSFET (LDMOST) structure is designed with n-type charge compensation layer embedded in the p−-substrate near the drain to suppress substrate-assisted depletion effect that results from the compensating charges imbalance between the pillars in the n-type buried layer. A high electric field peak is introduced in the surface by the pn junction between the p−-substrate and n-type buried layer, which given rise to a more uniform surface electric field distribution by modulation effect. The effect of reduced bulk field (REBULF) is introduced to improve the vertical breakdown voltage by reducing the high bulk electric field around the drain. The new structure features high breakdown voltage, low on-resistance and charges balance in the drift region due to n-type buried layer.