Superconducting Logic Circuits Research Articles

Long-range phase coherence and tunable second order φ0-Josephson effect in a Dirac semimetal 1T-PtTe2

Superconducting diode effects have recently attracted much attention for their potential applications in superconducting logic circuits. Several pathways have been proposed to give rise to non-reciprocal critical currents in various superconductors and Josephson junctions. In this work, we establish the presence of a large Josephson diode effect in a type-II Dirac semimetal 1T-PtTe2 facilitated by its helical spin-momentum locking and distinguish it from extrinsic geometric effects. The magnitude of the Josephson diode effect is shown to be directly correlated to the large second-harmonic component of the supercurrent. We denote such junctions, where the relative phase between the two harmonics can be tuned by a magnetic field, as ‘tunable second order φ0-junctions’. The direct correspondence between the second harmonic supercurrents and the diode effect in 1T-PtTe2 junctions at relatively low magnetic fields makes it an ideal platform to study the Josephson diode effect and Cooper quartet transport in Josephson junctions.

High-density superconductive logic circuits utilizing 0 and π josephson junctions

Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics’ scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100×in the SCE chips.

Optimization of Adiabatic Superconducting Logic Cells by Using π Josephson Junctions

Adiabatic superconducting logic circuits can ensure the practical implementation of operations with the energy dissipation below the Landauer limit. However, applications of the existing solutions are limited because of two contradictory requirements of a high energy efficiency and a sufficiently fast response of devices. Josephson junctions with a negative critical current (π junctions) allow one to obtain a certain form of the potential energy of superconducting circuits and, as a result, a practically required degree of control of dynamic processes in the proposed reversible logic cells. The features of the current transport and balance of Josephson phases in circuits with π junctions make it possible to improve the coupling between the parts of a reversible computer by a factor more than 2. At the same time, the continuous evolution of the state is ensured at higher critical currents and higher characteristic voltages of the main Josephson junctions of adiabatic superconducting logic cells, which allows an increase in the response rate.

YBa$_{2}$Cu$_{3}$O$_{7-\delta }$Single Flux Quantum Flip Flop Directly Written With a Focused Helium Ion Beam

Superconducting logic circuits based on low transition temperature (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) are attractive due to their intrinsic low power consumption and high operating frequency. They have a wide variety of applications (particularly in future computing), but are difficult to use because they require cooling with liquid helium to operate. The current high T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> logic circuit based on YBa <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7-δ</sub> (YBCO) already has the ability to operate at a temperature above 4 K. However, this material is difficult to integrate into large-scale circuits by the traditional YBCO junction fabrication process. The limits of fabrication methods are the bottleneck stifling this material's potential for integration into logic circuits. As such, in this paper we aim to advance the state of the art in junction fabrication technology. Here we report the demonstration of a high T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> superconducting single flux quantum (SFQ) circuit made by a focused helium ion beam that is easily fabricated and can readily be incorporated into a large-scale integration with nano-scale junctions for future applications. An inductively coupled readout superconducting quantum interference device (SQUID) is employed to reduce the circuit complexity. The circuit parameters and performance are discussed.

Low-power high-speed half-flux-quantum circuits driven by low bias voltages

Half-flux-quantum (HFQ) circuits store and propagate half-flux quanta. The basic circuit element is a 0-π SQUID, which is a superconducting quantum interference device with a conventional Josephson junction (0-junction) and a π-shifted ferromagnetic junction (π-junction). A 0-π SQUID achieves a small critical current in the absence of an external magnetic field, thus reducing power consumption. It is easy to set up 0-0-π SQUIDs with two 0-junctions and a π-junction which serves as a π phase-shifter. We simulated 0-0-π SQUID-based HFQ circuits driven by low bias voltages, referred to as LV-HFQ circuits. In these circuits, shunt resistors are not required for switching junctions because there is no hysteresis in the current–voltage characteristics of 0-0-π SQUIDs. We estimated the power consumption and maximum operating frequency of an HFQ Josephson transmission line based on 0-0-π SQUIDs. When operating at 43.5 GHz, the power dissipation of a single element composed of a 0-0-π SQUID and a bias resistor fell to about 0.165 nW when biased at 60 μV. The LV-HFQ circuit is potentially more power-efficient than all other currently available superconducting logic circuits.

Miniaturization of the Superconducting Memory Cell via a Three-Dimensional Nb Nano-superconducting Quantum Interference Device.

Scalable memories that can match the speeds of superconducting logic circuits have long been desired to enable a superconducting computer. A superconducting loop that includes a Josephson junction can store a flux quantum state in picoseconds. However, the requirement for the loop inductance to create a bistate hysteresis sets a limit on the minimal area occupied by a single memory cell. Here, we present a miniaturized superconducting memory cell based on a three-dimensional (3D) Nb nano-superconducting quantum interference device (nano-SQUID). The major cell area here fits within an 8 × 9 μm2 rectangle with a cross-selected function for memory implementation. The cell shows periodic tunable hysteresis between two neighboring flux quantum states produced by bias current sweeping because of the large modulation depth of the 3D nano-SQUID (∼66%). Furthermore, the measured current-phase relations (CPRs) of nano-SQUIDs are shown to be skewed from a sine function, as predicted by theoretical modeling. The skewness and the critical current of 3D nano-SQUIDs are linearly correlated. It is also found that the hysteresis loop size is in a linear scaling relationship with the CPR skewness using the statistics from characterization of 26 devices. We show that the CPR skewness range of π/4-3π/4 is equivalent to a large loop inductance in creating a stable bistate hysteresis for memory implementation. Therefore, the skewed CPR of 3D nano-SQUID enables further superconducting memory cell miniaturization by overcoming the inductance limitation of the loop area.

Heat flux capacity measurement and improvement for the test of superconducting logic circuits in closed-cycle cryostats

With the current progress of superconducting integrated circuits, circuit complexities have reached more than 100,000 Josephson junctions. At the laboratory environment, circuit tests are generally being conducted at liquid Helium environments. With the commercialization of the superconducting integrated circuit-based systems and/or price increase of liquid Helium, utilization of the closed-cycle systems will be inevitable. Even though it is possible to implement closed-cycle systems with quite substantial excess cooling powers after all the wirings and peripheral circuits, one point not to be overlooked is the power density at the superconducting chips. We have observed that the circuits designed for operation at liquid Helium bath have much higher power densities that exceed the heat flux capacities of closed-cycle cryocoolers. We have measured that the heat flux capacities of closed-cycle systems are about 0.1 W/cm${}^{2}$ when the chip is in vacuum. Thus, if the power density in any of the bias resistors are higher than these values, it is difficult to keep the chip in superconducting state. With the positive feedback from a local hot spot under current bias, the chip rapidly heats up due to Joule heating. To increase the limit of power density, we propose an encapsulation method that increases the heat flux capacity of the system. With the encapsulation, the heat flux capacity of the system is increased to about 0.4 W/cm${}^{2}$.

Energy Efficient Superconducting Neural Networks for High-Speed Intellectual Data Processing Systems

We present the results of circuit simulations for the adiabatic flux-operating neuron. The proposed cell with one-shot calculation of activation function is based on a modified single-junction superconducting quantum interferometer. In comparison, functionally equivalent elements of the artificial neural network (ANN) in the semiconductor-based implementations consist of approximately 20 transistors. Also in the article, we present the connecting synapse based on the adiabatic quantum flux parametron. These neurons and synapses allow constructing ANNs with a magnetic representation of information in the form of direction and/or magnitude of the magnetic flux in the superconducting circuit. We discuss the dissipation of energy during operations in the frame of the proposed concept. This value in superconducting neurons and synapses with sub-nanosecond timescale can be reduced down to 10 and 0.1 aJ, respectively. The use of the adiabatic superconducting logic circuits in our approach promises compatibility with superconducting quantum information processing systems.

Design methodology of single-flux-quantum flip-flops composed of both 0- and π-shifted Josephson junctions

A methodology for designing single-flux-quantum (SFQ) flip-flops composed of both conventional (0-) and π-shifted Josephson junctions is investigated. We investigated the implementation of a storage loop, which can store flux quantum and is indispensable to express binary logic states in superconductor logic circuits. As all SFQ flip-flops have storage loops, the investigated design methodology can be applied to their design. We designed several SFQ flip-flops composed of 0- and π-shifted Josephson junctions using the investigated design methodology. The performances of the designed SFQ flip-flops were quantitatively evaluated by using an analog circuit simulator which we developed. We confirmed the correct operation of various SFQ flip-flops composed of 0- and π-shifted Josephson junctions with wide operating margins. Moreover, we observed that the investigated design methodology is suitable for SFQ flip-flops with complementary outputs because a storage loop composed of both 0- and π-shifted Josephson junctions has a symmetric structure and the complementary output function can be realized by using the storage loop. Our investigation indicates that the number of Josephson junctions and static power consumption of a non-destructive read-out flip-flop with complementary outputs (NDROC) can be reduced to less than half of those of the conventional NDROC, which has two storage loops composed of 0-Josephson junctions, to realize the complementary output function. The investigated design methodology is expected to be applied to not only SFQ circuits but also other superconducting logic circuits and novel reconfigurable logic devices using programmable 0-π Josephson junctions.

Recent Progress of Superconducting Integrated Circuit Technologies Challenging the Limits in Low Power Consumption

Superconducting logic circuits, which utilize a single flux quantum as logical bit information, have outstanding properties as a logic circuit in terms of power consumption and operation speed. In this paper, recent progress of superconducting integrated circuit technologies, which aim the reduction of the power consumption of high-end computing systems and have potential to approach the physical limit of energy consumption in computation, will be reviewed.

Implementation of superconductor/ferromagnet/ superconductor π-shifters in superconducting digital and quantum circuits

Interrupting a superconducting loop with a thin ferromagnetic film creates a so-called π-Josephson junction that shifts the phase of a current flowing in the loop by 180°. A demonstration of the use of π-junctions in a variety of device structures suggests they could enable the development of a new class of superconducting logic circuits. High operation speed and low energy consumption may allow the superconducting digital single-flux-quantum circuits to outperform traditional complementary metal–oxide–semiconductor logic. The remaining major obstacle towards high element densities on-chip is a relatively large cell size necessary to hold a magnetic flux quantum Φ0. Inserting a π-type Josephson junction1,2 in the cell is equivalent to applying flux Φ0/2 and thus makes it possible to solve this problem3. Moreover, using π-junctions in superconducting qubits may help to protect them from noise4,5. Here we demonstrate the operation of three superconducting circuits—two of them are classical and one quantum—that all utilize such π-phase shifters realized using superconductor/ferromagnet/superconductor sandwich technology6. The classical circuits are based on single-flux-quantum cells, which are shown to be scalable and compatible with conventional niobium-based superconducting electronics. The quantum circuit is a π-biased phase qubit, for which we observe coherent Rabi oscillations. We find no degradation of the measured coherence time compared to that of a reference qubit without a π-junction.

Superconductive combinational logic circuit using magnetically coupled SQUID array

In this paper, we propose the development of superconductive combinational logic circuits. One of the difficulties in designing superconductive single-flux-quantum (SFQ) digital circuits can be attributed to the fundamental nature of the SFQ circuits, in which all logic gates have latching functions and are based on sequential logic. The design of ultralow-power superconductive digital circuits can be facilitated by the development of superconductive combinational logic circuits in which the output is a function of only the present input. This is because superconductive combinational logic circuits do not require determination of the timing adjustment and clocking scheme. Moreover, semiconductor design tools can be used to design digital circuits because CMOS logic gates are based on combinational logic. The proposed superconductive combinational logic circuits comprise a magnetically coupled SQUID array. By adjusting the circuit parameters and coupling strengths between neighboring SQUIDs, fundamental combinational logic gates, including the AND, OR, and NOT gates, can be built. We have verified the accuracy of the operations of the fundamental logic gates by analog circuit simulations.

Design infrastructure for Rapid Single Flux Quantum circuits

Cryoelectronic integrated circuits based on Rapid Single Flux Quantum (RSFQ) technology are promising candidates for realizing systems exhibiting very high performance in combination with very low-power consumption. Like other superconductive logic circuits, they are characterized by a high switching speed. Their unique feature consists in the particular representation of binary information by means of short transient voltage pulses. The development of RSFQ circuits and systems requires a comprehensive design approach, supported by appropriate tools. Within the recent years, a dedicated design infrastructure has been developed in Europe in close association with a foundry for digital RSFQ integrated circuits. As a result, RSFQ technology has matured to such a level that engineering efforts enable the development of integrated circuits. In the contribution, the basic features of the RSFQ circuit design are addressed within the context of technical and infrastructural issues of implementation from a European perspective.

Classical and Quantum Operation Modes of the Reversible Josephson-Junction Logic Circuits

One of the most important features of the quantum computing circuits that distinguishes them from the traditional computational models is their full, physical and logical, reversibility at all stages of the calculations. This makes the large-scale architecture of potential quantum and classical reversible computers quite similar. The goal of this work is to analyze this similarity in the case of reversible superconducting logic circuits based on the recently suggested elementary gate, the nSQUID. Specifically, we present the results of numerical simulations and some limited measurements of a reversible 8-bit circular shift register fabricated at HYPRES, Inc., and working in the classical mode. The measured energy dissipation per bit operation per nSQUID is still about 20 times higher than the thermodynamic reversibility threshold of k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> TIn 2 at T ap 4 K. We also discuss qualitatively operation of the reversible circuits of galvan- ically-coupled nSQUIDs in the quantum mode which provides the basis for implementation of "flying" superconducting qubits. Such qubits have several attractive features for Josephson-junction quantum logic devices beyond the single- or two-qubit circuits.

Delay Analysis of Self-Timing-Aligned Clock Synchronization Technique for Superconductive SFQ Logic Circuits

Delay analysis for superconductive Single Flux Quantum (SFQ) logic is performed for Self-Timing-Aligned Clock Synchronization Technique (STAC). With its pipelined-structure, the SFQ generates and propagates pulses that are to be processed sequentially through serial-connected functional logic blocks, and thus it is critical to acquire a ultra-high-speed and exactly synchronized clock/control signals with a few pico-second resolution. Both passive and Josephson-Junction circuits are investigated for the delay control. These delays, being connected in parallel with input line, and to the clocked-power/control node, produce a self-timing-aligned synchronization. Ways to achieve precision delays are seek by using Mo resistors along with junction inherent capacitors. Both current margins for the bias and critical timing information for the maximum throughput are also investigated. Layouts for the test SFQ circuits, such as D- and RS-flip-flops are done with XIC, and verifications are done through WRSpice with Hypres process parameters.

Superconductive logic circuits constructed by the use of two thresholds of SQUID

This paper proposes a method for constructing superconductive logic circuits by actively using two thresholds in a superconducting quantum interference device (SQUID). First, it is demonstrated that the input–output characteristics of a SQUID with multiple inputs can be represented as a two-threshold logic function. Next, a SQUID structure is shown in which all of the input currents have the same significance and the threshold current can be varied without varying the characteristics of the Josephson junction. Each input is weighted by adjusting the internal impedance rather than the input current, and the SQUID thresholds are varied using the value of the steady current applied to an additional input. Finally, it is explained that when logic functions of two to four variables are realized using such SQUIDs, the number of logic functions that can be realized with a single SQUID is much greater than when an existing method is used, and the operating regions are reduced only slightly. © 2005 Wiley Periodicals, Inc. Syst Comp Jpn, 36(2): 42–50, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.20136

Rapid single-flux quantum logic using π-shifters

We have found that the size of some rapid single-flux quantum (RSFQ) logic cells based on conventional 0-type Josephson junctions can be significantly reduced by using a π-type junction as a phase shifter in passive (nonswitching) mode. In comparison with the recently suggested active (switching) π-junctions mode, the passive mode offers much greater operation margins for their critical current Icπ. This gives π-junctions a chance to be implemented in RSFQ designs in the near future. As an example, we have simulated the operation of a toggle flip flop with zero-geometrical inductance of the fluxon storage loop. Simulations show that the parametric inductance of the π-junction and its normal resistance Rn form a low-pass filter, which sets the low limit for π-junctions IcπRn product, but offers a wide range of variations of the other parameters. The possible reduction of RSFQ cell size by using π-junctions opens the way to scale superconducting logic circuits down to the submicron dimensions.

Performance of MVTL logic at multi-GHz frequencies

Demonstrating superconductive logic circuits at high speeds is crucial in gaining acceptance by potential users. We are taking an integrated approach toward demonstrating the potential of such circuits. Issues addressed include the effects that layout have upon a circuit and gate (particularly in scaling down the size of gates to increase density), testing limitations, designing for minimum crosstalk and ground ripple, and fundamental limitations to gate performance. In this paper, we report our progress in resolving and understanding these issues. Circuits such as shift registers were used to understand the influence of layout on performance, circuits such as gate chains and punchthrough detectors to explore fundamental gate limitations. We also report on signal processing circuits of several hundred gates tested at clock frequencies up to several hundred MHz and the relationship between these results and the fundamental gate performances.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Experimental evaluation of some rapid single flux quantum cells

Some basic cells in the rapid single-flux quantum (RSFQ) family of superconductive logic circuits were studied. An input stage, a buffer, and an OR gate were simulated and laid out for a standard niobium-based fabrication process. The resulting circuits perform properly for clock speeds up to 1 GHz. For the simpler circuits tested, the measured margins are wide, consistent with simulations, and not very dependent on clock speed. However, margin decreases with increased circuit complexity. The input stage converts a rising edge into an SFQ pulse, which has a small amplitude and narrow width in time. On the present circuits, these pulses are about 200 mu V in amplitude and 10 ps in width. To facilitate measurement, the authors have chosen as the output an asymmetrical superconducting quantum interference device (SQUID) consisting of two Josephson junctions. It converts SFQ pulses into 2.5 mV latching output levels on chip. By inductively coupling SFQ pulses into the SQUID loop, DC current isolation between the RSFQ circuit-under-test and the output stage is provided. The SQUID was optimized for 2 GHz operations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Proposal of dual-powered superconducting logic circuits

A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. Logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.