Super Self-aligned Process Technology Research Articles

Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops

This paper presents two circuit techniques for highspeed operation of a master-slave toggle flip-flop circuit (MSTFF). One circuit reduces the gain in latching circuits, and the other uses the transient current of the emitter followers to boost the switching speed. Both the SPICE simulations and the measured results for static 1/8 frequency dividers fabricated using 0.5-/spl mu/m super self-aligned process technology (SSTIC) show that the maximum operating speed of our MS-TFF's is 10% and 30% faster than that of conventional ones. By applying these technologies, 19.1-GHz and 22.4-GHz Si bipolar static frequency dividers have been fabricated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology

We have designed and fabricated a high-bit-rate, high-input-sensitivity decision circuit for future optical communication systems using an advanced super self-aligned Si bipolar process technology (SST-1C). The SST-1C transistors are fabricated by 0.5-/spl mu/m photolithography. The peak cut-off frequency of a typical transistor is 31 GHz at a collector-emitter voltage of 3 V. The circuit design involves the optimization of individual transistor sizes to boost the speed and the adoption of a wide-band preamplifier to enhance input sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mV/sub p-p/. An extremely high input sensitivity of 15 mV/sub p-p/ and a wide phase margin of 260/spl deg/ at 10 Gb/s are achieved. >

Deep submicrometer super self-aligned Si bipolar technology with 25.4 ps ECL

A new deep submicron double-poly self-aligned Si bipolar technology has been developed using a 0.3-/spl mu/m design rule, a collector polysilicon trench electrode, and oxide-filled trench isolation. This technology is called "High-Performance Super Self-Aligned Process Technology" or HSST. 0.3-/spl mu/m minimum patterning is achieved by electron-beam direct writing technology. The HSST bipolar transistor is 2.5 times smaller than the previous 1-/spl mu/m SST-1B. Owing to its horizontal reduction and an f/sub T/ of 22.3 GHz at V/sub ce/=1 V, the ECL gate attains 25.4 ps/G at 1.58 mA, which is a 30% improvement on the SST-1B. By including parasitic capacitances of the base polyelectrode and polyresistors, the ECL delay time is accurately simulated for low-power operation. It is shown that the HSST is a very promising technology for the development of future high-speed communication systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-speed analogue neural-network LSI employing super-selfaligned Si bipolar process technology

A high-speed analogue neural-network LSI is developed using super selfaligned Si bipolar process technology. The LSI contains four neurons and 16 electrically-modifiable synaptic weights. Neural processing is demonstrated with ‘exclusive OR’ logic at a speed of 150 megapatterns per second.

Cell processing LSIs for 2.4 Gbit/s SDH-based ATM transmission system

Introduces cell processing large-scale integrated circuits (LSIs) suitable for byte-oriented systems operating at 2.4 Gbit/s. The LSIs are based on a newly proposed cell delineation circuit which uses a pipeline processing technology to realise byte-by-byte shift operations, an error-detect and error-correct circuit and a descrambling circuit. Prototype LSIs, constructed with a super-selfaligned process technology (SST), are tested at up to 3.7 Gbit/s. >

A circuit design for 2-Gbit/s Si bipolar crosspoint switch LSIs

An 8*8 and an expandable 16*16 crosspoint switch LSI utilizing a new circuit design and super self-aligned process technology (SST-1A) are discussed. The LSIs successfully switched with a bit error rate of less than 10/sup -9/ at 2.5 Gb/s using a 2/sup 9/-1 pseudorandom NRZ sequence. Pulse jitter was limited to less than 80 ps at 1.2 Gb/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSIs have an ECL-compatible interface, -4-V and -2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8*8 LSI and 2.8 W for the expandable 16*16 LSI. >

A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantation: S. Konaka, E. Yamamoto, K. Sakuma, Y. Amemiya, T. Sakai (NTT Corp., Kanagawa, Japan) IEEE Trans. Electron Devices (USA), vol. 36, no. 7, p. 1370–1375 (July 1989)

A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantation: S. Konaka, E. Yamamoto, K. Sakuma, Y. Amemiya, T. Sakai (NTT Corp., Kanagawa, Japan) IEEE Trans. Electron Devices (USA), vol. 36, no. 7, p. 1370–1375 (July 1989)

A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantation

A super self-aligned process technology, SST-1B, which is an advanced version of the previously proposed SST-1A in high-speed Si bipolar LSIs is discussed. A selectively ion-implanted collector (SIC) process and bird's-beak-free isolation process are utilized. The SIC process is designed to improve shallow base-collector profiles in the intrinsic region. It reduces base width and intrinsic base resistance, and suppresses the base push-out effect (Kirk's effect) in high-current operations. The SIC profile is easily controlled by 150-200 keV phosphorous ion implantation at the base-collector junction. Using these processes, SST-1B has achieved a high cutoff frequency of 21.1 to 25.7 GHz and a fast switching delay of 20.5 ps/G for nonthreshold logic and 34.1 ps/G for emitter-coupled logic. SST-1B has potential applications to 50-ps/G logic LSIs and 10-GHz SSIs. Device simulation indicates that it is possible to achieve a cutoff frequency of 40-50 GHz in a future scaled-down Si bipolar transistor with a 40-nm base and graded collector. >

2 Gbit/s, 16×16 expandable high-speed space-division-switch LSI using SST

A Si bipolar 2 Gbit/s 16×16 high-speed space-division-switch LSI is described. High-speed operation of 2 Gbit/s and low-power dissipation of 2.8 W are achieved by adopting a new expandable structure, a very low voltage swing-differential bipolar circuit design and a super self-aligned process technology (SST-1A). This LSI is applicable to future B-ISDN HDTV switching systems.

18-GHz 1/8 dynamic frequency divider using Si bipolar technologies

Circuit technology to achieve high-speed frequency dividers using Si bipolar devices is studied. A novel circuit configuration based on regenerative frequency division was proposed and analyzed. It is determined that the 3-dB-down bandwidth of the open loop of the novel circuit configuration is three times higher than that of the conventional circuit and that it operates almost up to the f/sub T/ of the transistor. A 1/8 dynamic divider using this novel circuit configuration was fabricated with advanced super self-aligned process technology (SST-1B). The divider operates between 4.6 and 18 GHz. It is noted that the circuit technology and process technology described are applicable to very-high-speed prescalers for satellite communication systems and high-speed measuring equipment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An 8-bit 2-ns monolithic DAC

An 8-bit resolution ultrahigh-speed monolithic digital-to-analog converter (DAC) is fabricated using super self-aligned process technology. In order to improve dynamic accuracy, which is determined by settling speed, clock feedthrough noise, and glitch, a number of circuit technologies are developed including a rise- and fall-time control switch driver, a low-noise flip-flop, and a differential buffer configuration. In addition, a chip assembly technology using a multilayer ceramic substrate is developed. The DAC exhibits a settling time to 8-bit accuracy of about 2 ns, a maximum conversion rate of 1 GHz, a glitch energy of 2 ps-V, and a 10-bit linearity error accuracy without trimming.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

43-ps 5.2-GHz macrocell array LSIs

A family of bipolar macrocell array LSIs has been developed which has a basic delay of 43 ps/CML and a toggle frequency of 5.2 GHz/flip-flop. This family uses a cascaded-differential and single-ended CML circuit and a highly advanced super self-aligned process technology (SST-1B) which uses a selectively ion-implanted collector technology based on SST-1A. Using the macrocell array LSIs, performances of 1.2 ns/1.2 W for a 6-bit multiplier, and 4.3 ns/3 W for a 16-bit multiplier have been achieved. >

A 50-ps 7 K-gate masterslice using mixed cells consisting of an NTL gate and an LCML macrocell

A 7 K-gate bipolar masterslice providing high-speed gates as well as highly functional cells has been developed. A basic mixed cell consisting of both a nonthreshold logic (NTL) gate and an LCML macrocell is introduced. A 1-/spl mu/m-rule super self-aligned process technology (SST-1A) is adopted in combination with three-level metallization technology. A basic NTL gate delay of 50 ps has been achieved with a power dissipation of 1.84 mW. For flip-flop (FF) performance using a macrocell, a toggle frequency of up to 2.6 GHz is obtained with 3.78 mW/FF. For application, a 24-bit parallel multiplier having a multiplication time of 12.8 ns is customized with a power dissipation of 5.1 W.

An 86 K component bipolar VLSI masterslice with a 290-ps loaded gate delay

A very large-scale integrated (VLSI) bipolar masterslice has been demonstrated. This masterslice has a loaded three-input ECL gate delay of 290 ps and an unloaded gate delay of 164 ps at a power dissipation of 1.5 mW/gate. It is fabricated by using 1.5-/spl mu/m rule super self-aligned process technology (SST), 2-/spl mu/m-wide deep U-groove isolation, and a fine 5-/spl mu/m pitch three-level metallization process. The authors describe its process features, cell design, chip structure, experimental results, and applications.

DC–coupled broadband and gain controllable monolithic amplifier circuits

AbstractThis paper will describe a method for broadening the bandwidth of gain controllable monolithic amplifier circuits for the purpose of the application to the repeater circuits in the Gb/s optical transmission systems. The gain controllable differential amplifier circuit exhibits narrower bandwidth because of larger parasitic capacitance components in comparison with basic differential amplifier circuits due to the complicated circuit configuration to control the gain. Also, when the peaking method for broadening the bandwidth is applied, the peaking amounts exceed the optimum value and becomes unstable in the low‐gain operation even if the peaking amounts are optimized for the high‐gain operations. In this paper, a new gain controllable amplifier circuit using the bias current dependency of differential resistance of diodes is proposed. Furthermore, the circuit is fabricated by using the Si Bipolar Super Self‐Aligned process Technology (SST). A broadband characteristic of 1.6 GHz bandwidth and 29‐dB gain controllable width has been obtained. These are sufficient for the application to the Gb/s optical repeater circuits.

A Design and Packaging Technique for a High-Gain, Gigahertz-Band Single-Chip Amplifier

Equalizing amplifiers for gigabit optical fiber transmission systems requires a 65-dB gain (S21) with a gigahertz bandwidth. However, this gain has the potential to cause significant parasitic oscillation. Consequently, developing a useful stabilization design technique is a very important factor in attaining practical design. In this paper, stabilization design techniques are described for circuit configurations, packaging, and stability assessment. In addition, fabrication results of amplifier IC based on bipolar super self-aligned process technology (SST) and new wide-band high isolation package with coaxial-like 50-/spl Omega/ signal lines are also shown. A 65-dB gain, 1.3-GHz bandwidth single-chip amplifier has been successfully fabricated.

A 30-ps Si bipolar IC using super self-aligned process technology

A new 30-ps Si bipolar IC technology has been developed by scaling down a bipolar transistor's lateral geometry and forming shallow junctions. The n-p-n transistor has a 0.35-µm-wide emitter and a 1.57-µm-wide base region fabricated using super self-aligned process technology (SST) with 1-µm rule optical lithography. The f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> values achieved for this device are 13.7 GHz at a collector-emitter voltage of 1 V and 17.1 GHz at 3 V. Propagation delay times (fan-in = fan-out = 1) of 30 ps/gate at 1.48 mW/gate for nonthreshold logic and 50 ps/ gate at 1.46 mW/gate for low-level current mode logic have been achieved.

Monolithic integrated CMI coder and decoder for gigabit optical links

The high-speed performance of a monolithic integrated CMI coder and decoder, which are fabricated using super self-aligned process technology, is described. The maximum line rate is 3.07 Gbaud. The power consumptions of the coder and decoder are 0.54 W and 0 43 W, respectively. An optical CMI transmission experiment was performed using an InGaAsP/InP laser diode, a Ge APD and an integrated receiver with a SAW filter retiming circuit. When the quality factor Q was 830 at 1.8 Gbaud, random jitter was below 0.7°. In addition, it was confirmed that a clock signal can be extracted from any input data.

High-speed and precise monolithic multiplier with radiation hardness using silicon bipolar SST

A high-speed and precise monolithic analogue multiplier with radiation hardness for high-speed onboard modems has been developed using Si-bipolar SST (super self-aligned process technology). The developed multiplier achieves an amplitude error of less than 0.2 dB p-p and a phase error of less than 2 degrees p-p up to 1 GHz. Moreover, radiatio hardness tests have proved the multiplier has a total dose. immunity up to 106rad (Si).

Design and application of a 2500-gate bipolar macrocell array

A very high-speed 2500-gate Si bipolar macrocell array has been developed using a novel macrocell design approach and a 1-/spl mu/m rule advanced super self-aligned process technology (SST-1A). Using this macrocell array, a 16-bit parallel multiplier is designed and fabricated. The sophisticated circuit design of the macrocell array approach permits this complex function, which is equivalent to having 3024 NOR gates, using only 70% of the total of 756 internal cells. Consequently, a fast multiplication time of 7.5 ns is achieved with a 2.07-W power dissipation. Excellent performance with an average gate delay of 120 ps and average power dissipation of 0.365 mW is demonstrated for an equivalent NOR gate.