Super Cascode Research Articles

Methodologies of Cascading to Realize High-Voltage Cascaded Super Cascode Power Switch

Methodologies of Cascading to Realize High-Voltage Cascaded Super Cascode Power Switch

Recent Trends on MOSFET based Cascode Current Mirrors: An Analytical Survey

To produce copy of current flowing through active devices, from one end to other end of the circuit, current mirrors (CM) are used irrespective of loading effect. It’s indispensable part of an analog and mixed signal system including wide range of applications. In this paper various cascode current mirror circuits such as, an ultra-high compliance current mirror with low power consumption, a CM with extensive swing, a self-biased CM, and quasi-floating CM circuits are analyzed which includes: speed, power, input and output resistance, bandwidth etc. The comparison shows that ultra-high compliance cascode current mirror utilizes low voltage with relatively high frequency response and consumes less power while super cascode configuration is a good choice to obtain high output impedance for better performance, whereas quasi-floating gate MOS current mirror with resistive compensation can be used to enhance the circuit bandwidth. The various circuits are designed at 250 nm, 180 nm, and 130 nm CMOS technologies for justification of performance.

A high output resistance, wide bandwidth, and low input resistance current mirror using flipped voltage follower cell

AbstractThe paper proposes a current mirror designed using the current sensor structure of class‐AB flipped voltage follower cell at the input stage and super cascode structure at the output stage. The proposed current mirror offers low input resistance due to the current sensor at the input stage and high output resistance due to super cascode configuration at the output stage. The proposed current mirror offers a good dynamic range of 0 to 300 μA with less copying error of 0.54%, wide bandwidth of 319.8 MHz, high output resistance of 19.8 GΩ, and low input resistance of 161.34 Ω. The proposed current mirror is designed using BSIM3V3 180‐nm CMOS technology and simulated using spectre in the Cadence Virtuoso analog design environment at room temperature. The Cadence Virtuoso layout XL editor has been used to design the physical layout of the proposed current mirror. The pre‐layout and post‐layout simulation results of the proposed current mirror have been shown to validate its performance. The Monte Carlo analysis has also been performed to analyze the effects of process variations and mismatches on the performance of the proposed current mirror.

Bidirectional Solid-State Circuit Breaker Using Super Cascode for MV SST and Energy Storage Systems

Solid-state transformers (SSTs) are developing as highly efficient interfaces in renewable energy, transport, and energy storage systems (ESSs). However, performance limitations, such as overvoltage sensitivity and fault handling capabilities, have slowed widespread adoption. Although SSTs are developing added capabilities for fault management, the required response speed and overdesign introduces added costs, particularly in protection of ultralow inductance systems, such as those sourced by ESSs. With increased use of power electronics, the power distribution systems are speeding up having shorter fault propagation delays and higher fault currents. This creates a need for alternative approaches to MV system protection. This article describes a bidirectional solid-state circuit breaker (BSSCB) based on a new SiC SuperCascode power switch, and a multilayered transient absorption network. This article studies transient heat transfer in the switch and provides a redefinition of the fuse curve as applied to the BSSCB suitable for digital control. This article identifies critical fault issues, discusses the impact on critical design points of the SuperCascode for a BSSCB, and provides design calculations for a complete 10-kV/300-A/3 X breaker, including the SuperCascode module. A scaled 6-kV/10-A/7 X SuperCascode is fabricated and tested to demonstrate switch response of <60 ns with fault isolation in 200 ns.

Comparison of Fast and Reliable Zero-Voltage Detection Topologies

In this article, three different topologies for a zero-voltage detection (ZVD) are introduced and compared. The ZVD is used to detect a zero-voltage condition (ZVC) across a medium-voltage (MV) switch. This switch can either consist of a single semiconductor device or several devices connected in series. Therefore, the ZVD must be able to withstand the same MV as the switch and at the same time be able to measure a low voltage (LV) across the switch with high reliability and accuracy. First, an emitter follower with an MV metal-oxide semiconductor field-effect transistor ( mosfet ) is introduced as the most trivial ZVD. Second, a current source with silicon carbide (SiC) Schottky barrier diodes to block the MV is introduced. Finally, an emitter-follower cascode using a silicon (Si) SiC super cascode of an LV mosfet and several junction field-effect transistors connected in series to block the MV is introduced. The second and third typologies can be scaled easily to any desired blocking voltage. For each topology prototype, test results are discussed. Their advantages and the corresponding measurement results as well as the application of the different topologies in a 5-MW dual-active bridge converter conclude this work.

Light controlled (super) cascode, LC(S)C, a power device with optical turn-on and -off

ABSTRACTThe proposed light-controlled cascode is a power electronic device (or circuitry) which can be turned-on and -off by optical excitation. In contrast to the light-triggered thyristor, which can optically be turned-on but not -off, the proposed device allows optical turn-on and -off. Also, it allows a scalability of the blocking voltage by the extension to a light-controlled supercascode [1] which is also shown. After a brief theoretical consideration experimental set-ups will be presented and measurements are shown. Due to the difficulty to buy appropriate devices required for the experimental set-ups some compromises were necessary. Therefore, these first experiments show a very slow switching behaviour. However, this could become speeded up by an optimized photodiode made from wide band gap semiconductor material. In spite of these compromises pulses with a power of 1 kW were turned-on and – off by the experimental set-up. However, this device is far away from being ready for series production but the feasibility is demonstrated and the potentials are shown.

A Study on Fastening the Switching Speed for Wide Bandgap Semiconductor Based Super Cascode

The Super Cascode is a series connected structure with a normally-off low voltage Si-MOSFET and multiple normally-on wide bandgap semiconductors. It has low switching losses compared with silicon based bipolar devices, and low on-resistance and low cost compared with other single high voltage normally-off wide bandgap semiconductor devices. In practice, however, there are inevitable parasitic inductances, which result in the increase of switching losses. The method is proposed to eliminate the common-source inductances (CSIs), such as using stack-die configuration with each device and adding an additional inductance in the gate loop of Si-MOSFET. It is numerically shown that the rise and fall times of the proposed method were 33.5% and 7.2% faster than the conventional one, respectively.

Low voltage high performance bulk driven quasi-floating gate based self-biased cascode current mirror

A low voltage high performance self-biased cascode current mirror in terms of output resistance and bandwidth is proposed in this paper. The proposed current mirror enhances the output resistance in range of mega ohms and also shows a significant improvement in bandwidth compared to prior arts. The current mirror is designed using bulk-driven technique which helps it to operate at very low supply voltage of ±0.2V. To achieve high output resistance, the proposed current mirror uses the super cascode stage at its output. Furthermore, an external capacitor is used which accounts for increasing the bandwidth. Small-signal analysis carried proves the improvement achieved by proposed architecture. The current mirror operates well for wide input current range from 0 to 200μA with good linearity and shows the bandwidth of 415MHz. The observed input and output resistance is 300Ω and 212MΩ respectively. Further, the THD and mismatch analysis is carried to prove the robustness of proposed current mirror. The complete analysis of proposed current mirror is shown using HSpice simulations on UMC 0.18μm technology.

Low Voltage High Output Impedance Bulk-Driven Quasi-Floating Gate Self-Biased High-Swing Cascode Current Mirror

A low voltage self-biased high-swing cascode current mirror using bulk-driven quasi-floating gate MOSFET is proposed in this paper. The proposed current mirror bandwidth and especially the output impedance show a significant improvement compared to prior arts. The current mirror presented is designed using bulk-driven and bulk-driven quasi-floating gate N-channel MOS transistors, which helped it to operate at very low supply voltage of $${\pm }0.2\,\hbox {V}$$±0.2V. To achieve high output resistance, the current mirror uses regulated cascode stage followed by super cascode architecture. The small-signal analysis carried out proves the improvement achieved by proposed current mirror. The current mirror circuit operates well for input current ranging from 0 to $$250\,{\upmu }\mathrm{A}$$250μA with good linearity and shows the bandwidth of 285 MHz. The input and output resistances are found as $$240\,\Omega $$240Ω and $$19.5\,\hbox {G}\Omega $$19.5GΩ, respectively. Further, the THD analysis and Monte Carlo simulations carried prove the robustness of proposed current mirror. The complete analysis is done using HSpice on UMC $$0.18\,\upmu \mathrm{m}$$0.18μm technology.

A very high performance compact CMOS current mirror

This paper proposes a very high performance current mirror (CM), where output current accurately copies the input current without carrying any offset component. Compact implementation of Garimella et al. CM structure has been combined with super cascode configuration to achieve the proposed very high performance CM. The proposed CM offers extremely high output resistance, very low input resistance and high degree of copying accuracy over a wide operating current range. Small signal analysis is carried out to validate the performance characteristics of the circuit. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology, using a single supply voltage of 1.5 V. The circuit is shown to have high current copying accuracy for a range of (0---500 µA) with an error less than 0.0016 % and has no offset current at the output side. The robustness of the proposed CM against the variations in device parameters and temperature changes has been reflected in simulations by carrying Monte Carlo and temperature analysis. The simulation results show that the proposed circuit provides very high output resistance of 55.76 G? and a very low input resistance of 0.07 ?.

Balancing Circuit for a 5-kV/50-ns Pulsed-Power Switch Based on SiC-JFET Super Cascode

In many pulsed-power applications, there is a trend to modulators based on semiconductor technology. For these modulators, high-voltage and high-current semiconductor switches are required in order to achieve a high pulsed power. Therefore, often, high-power IGBT modules or IGCT devices are used. Since these devices are based on bipolar technology, the switching speed is limited, and the switching losses are higher. In contrast to bipolar devices, unipolar ones (e.g., SiC JFETs) basically offer a better switching performance. Moreover, these devices enable high blocking voltages in the case where wide-band-gap materials, for example, SiC, are used. At the moment, SiC JFET devices with a blocking voltage of 1.2 kV per JFET are available. Alternatively, the operating voltage could be increased by connecting <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$N$</tex></formula> JFETs and a low-voltage MOSFET in series, resulting in a super cascode switch with a blocking voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$N$</tex> </formula> times higher than the blocking voltage of a single JFET. For the super cascode, auxiliary elements are required for achieving a statically and dynamically balanced voltage distribution in the cascode. In this paper, a new balancing circuit, which results in faster switching transients and higher possible operating pulse currents, is presented and validated by measurement results.