Sum-of-powers-of-two Research Articles

Using Particle Swarm Optimization for design comb compensator with magnitude response synthetized as sine function

Comb compensator improves the passband characteristic of comb filter, i.e. decreases the comb passband droop. This paper presents one method for a comb compensator design with the magnitude response synthetized as sine function. The parameter of design is the amplitude of sine function denoted as A. The goal is to find the amplitude of sine function A for each value of comb parameter, K, K=1, …,5, where K is the number of the cascaded comb filters. First the optimum values of the amplitude of sinusoidal function A, for each value of K, K=1, …,5 are obtained using Particle Swarm Optimization (PSO). It is demonstrated that the obtained values A practically do not depend on the decimation factor M, for M>10. In next step the obtained values of the parameter A are presented as sum of powers of two (SPT) to get a multiplierless design. The method is illustrated with one example and compared with the methods from literature.

Optimized Design of FIR Filter Based On FPGA

Based on the field programmable gate arrays (FPGA), a low area and high speed FIR filter is proposed and designed. The multiplication modules were replaced by adders and shift registers in the proposed architecture. This is possible because a coefficient approximation is performed, using the algorithm that computes the coefficients like a sum-of-powers-of-two (SOPOT). Compared with the traditional method, the area of the 7-tap 12 bit FIR filter occupied is 75%smaller.

Oversampled DFT-Modulated Biorthogonal Filter Banks: Perfect Reconstruction Designs and Multiplierless Approximations

We propose a novel methodology for designing oversampled discrete Fourier transform-modulated uniform filter banks. The analysis prototype is designed as a Nyquist filter, whereas the synthesis prototype is designed to guarantee perfect reconstruction (PR) considering oversampling. The resulting optimization problem fits into the disciplined convex programming framework, as long as some convex objective function is employed, as the minimization of either the stop-band energy or the maximum deviation from a desired response. The methodology also accounts for near-PR multiplierless approximations of the prototype analysis and synthesis filters, whose coefficients are obtained in the sum-of-power-of-two (SOPOT) space. The quantized coefficients are computed using successive approximation of vectors, which is able to yield filters with a reduced number of SOPOT coefficients in a computationally efficient manner. The proposed methodology is especially appealing for supporting actual hardware deployments, such as modern digital transparent processors to be used in next-generation satellite payloads.

Design and Multiplierless Realization of Maximally Flat Sharpened-CIC Compensators

Polynomial sharpening is an efficient technique for improving folding band response of cascaded-integrator-comb (CIC) decimation filters. However, the sharpening of folding bands results in a high passband droop, which is intolerable in many applications. The droop can be reduced by connecting a symmetric finite-impulse-response filter called compensator in the cascade with the sharpened CIC (SCIC) filter. This brief presents a method for the design of such compensators, which is based on maximally flat error criterion. The compensator’s coefficients are obtained by solving a linear system of equations which is formed using a straightforward procedure. The coefficients obtained generally take real values. However, we show that for the SCIC filters incorporating integer or sum of powers of two (SPT) polynomial coefficients, and whose decimation factors are expressed as powers of two, the coefficients of corresponding maximally flat compensators are integers or SPT representable. For these types of SCIC filters, the optimum multiplierless structures of the compensators with three and five coefficients are described.

Design of FIR Hilbert transformers using prescribed subfilters and nested FT technique

In this article, a transformation (subfilter) for designing finite impulse response (FIR) Hilbert transformers (HTs) is proposed. With our approach, except simple search procedures, neither optimisation nor any filter design algorithm is needed to obtain the transformation. The proposed subfilter requires only two multipliers regardless of the subfilter order. For the frequency transformation design, the purpose of the subfilter is to provide a “rough” shape of the desired HT; the two coefficients of the subfilter can be implemented as the form of sum of power of two (SOPOT) with only a few bits, thus leading to a multiplierless realisation. Moreover, by applying the transformation on the subfilter again, a technique named as nested frequency transformation (nested FT) is introduced. This technique can further reduce the number of multipliers needed in the overall HT.

FPGA Implementation of FIR Filter using Various Algorithms: A Retrospective

This Paper is a review study of FPGA implementation of Finite Impulse response (FIR) with low cost and high performance. The key observation of this paper is an elaborate analysis about hardware implementations of FIR filters using different algorithm i.e., Distributed Arithmetic (DA), DA-Offset Binary Coding (DA-OBC), Common Sub-expression Elimination (CSE) and sum-of-power-of-two (SOPOT) with less resources and without affecting the performance of the original FIR Filter. .

Optimization of the Quantized Coefficients for DDFS Utilizing Polynomial Interpolation Methods

In this brief, a novel method to find the optimized quantized coefficients for direct digital frequency synthesizers (DDFSs) based on polynomial interpolation methods is introduced. First, a new method is introduced to find the spurious-free dynamic-range upperbound for DDFSs with a polynomial interpolation method, utilizing the discrete Fourier transform and the Chebyshev minimax problem. This method can be modified to obtain quantized coefficients by employing mixed-integer linear programming. In this problem, the polynomial coefficients are presented in a positive sum of powers of two (SPT) and unsigned integer forms. The proposed method is used to design the linear interpolation-based DDFSs with nonuniform segmentations. The VLSI realizations of the designs with nonuniform segmentations are provided, where it is shown that they have a smaller silicon area and higher clock frequencies compared with the state-of-the-art designs reported in literature.

DA-Based Efficient Testable FIR Filter Implementation on FPGA Using Reversible Logic

This paper discusses the FPGA implementation of finite impulse response (FIR) filters using a testable reversible logic-based design. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up table (LUT) accesses. The canonical signed digit (CSD) representation is used to represent the coefficients which are compared with sum-of-powers-of-two (SOPOT) technique of coefficients representation. Distributed arithmetic provides a multiplication-free method for calculating inner products of fixed-point data, based on table look-ups of pre-calculated partial products. The implementation results are provided to demonstrate a high-speed and low power proposed architecture. The proposed filter is implemented in very high speed integrated circuit hardware description language (VHDL) and verified via simulation. The reversible architecture scheme yields significantly reduced complexity, low power, and high speed features. The major concern with reversible gates is the reduction of garbage outputs and constant inputs. The proposed gate has less garbage outputs and constant inputs, which are important parameters for reversible designs. The proposed method offers average reductions of 30 % in the number of LUT, 42 % reduction in occupied slices and 38 % reduction in the number gates for low pass FIR filter implementation method. The proposed design shows 45 % improvement in performance as compared to existing one.

A New Algorithm for Non-Multiplier Approximation of Frequency Transformation for Two-Dimensional FRM Filters

In this paper, non-multiplier approximation of frequency transformation is examined. 2-D frequency response marking filters with sum of powers-of-two (SOPOT) coefficients are designed. The numbers of adders allocated to transformation coefficients are determined in the experiments so that the resulting 2-D filters preserve the stopband attenuation of the original 1-D prototype filters. Experimental results of 2-D wideband FIR filters with low arithmetic operations and computational complexity are presented.

Wideband Beamforming Based on Farrow Structure

In this paper, the principles of digital beamforming (DBF) and farrow structure are presented. Sum-of-powers-of-two (SOPOT) and cut-set retiming are used for saving the FPGA multiplier consumption and improving the running speed of farrow structure. A design example is given and the FPGA resource consumption saving is discussed also. The corresponding test results demonstrate the effectiveness of the fractional delay. With the fractional delay, it’s easy to realize wideband beam steering and digital beam forming.

Design of Linear-Phase Filter Banks with Multiplier-Less Lattice Structures

Abstract In this paper, a new multiplier-less algorithm is proposed for the design of perfectreconstruction linear-phase (PR LP) filter banks by using multiplier-less lattice structures. The coefficients in the multiplication operations have been replaced with limited number of additions and the computational complexity is reduced significantly. The property of perfection reconstruction, however, is preserved regardless the multiplier-less approximation of lattice structures in the factorization of polyphase matrix. The coefficients in the 2x2 rotation matrices of the lattice structures are expressed as sum-of-powers-of-two (SOPOT) coefficients in the parameterization processes. By using the multiplier-less rotation matrices, the unitary matrices are constructed for the lattice factorization of perfect-reconstruction linear-phase filter banks. Design examples of 5-channel and 8-channel multiplier-less linear-phase filter banks are included to validate the algorithm and implementation.

A SPT Treatment to the Realization of the Sign-LMS Based Adaptive Filters

The “sum of power of two (SPT)” is an effective format to represent filter coefficients in a digital filter which reduces the complexity of multiplications in the filtering process to just a few shift and add operations. The canonic SPT is a special sparse SPT representation that guarantees presence of at least one zero between every two non-zero SPT digits. In the case of adaptive filters, as the coefficients are updated with time continuously, conversion to such canonic SPT forms is, however, required at each time index, which is quite impractical and requires additional circuitry. Also, as the position of the non-zero SPT terms in each coefficient word changes with time, it is not possible to carry out multiplications involving the coefficients via a few fixed “shift and add” operations. This paper addresses these problems, in the context of a SPT based realization of adaptive filters belonging to the sign-LMS family. Firstly, it proposes a bit serial adder that takes as input two numbers in canonic SPT and produces an output also in canonic SPT, which is then extended to the case where one of the inputs is given in 2's complement form. This allows weight updating purely in the canonic SPT domain. It is also shown how the canonic SPT property of the input can be used to reduce the complexity of the proposed adder. For multiplication, the canonic SPT word for each coefficient is partitioned into non-overlapping digit pairs and the data word is multiplied by each pair separately. The fact that each pair can have at the most one non-zero digit is exploited further to reduce the complexity of the multiplication.

Design and Multiplierless Implementations of ECG-Based 1st Order Gaussian Derivative Wavelet Filter with Lattice Structures

In this paper, the 1st order Gaussian derivative wavelet function utilized in the design of some corresponding filter banks. Since the 1st order Gaussian derivative function has a similar shape to QRS complex part of the ECG, it can be used in QRS feature extraction. Using this characteristic of such wavelet function, the designed FIR wavelet filter banks can be realized in highly-efficient lattice structures which are easy to implement in two standard deviation values ( σ=1 and σ=2 ). The resulting lattice structures reduce the number of filter banks coefficients and this reduces, in turn the number of multiplications and improves the filter banks efficiencies as it reduces the number of computations performed. The resulting quantized multiplier values can also lead to multiplierless realizations using sum-of-power-of-two (SOPOT) method. FPGA implementations of such structures are achieved with less-complexity.

A novel approach for coefficient quantization of low-pass finite impulse response filter using differential evolution algorithm

Evolutionary computational techniques have been employed judiciously in various signal processing applications of late. In this paper, such an attempt has been made to design a low-pass linear-phase multiplier-less finite duration impulse response (FIR) filter using differential evolution (DE) algorithm. This particular evolutionary optimization technique has been explored to search the impulse response coefficients of the FIR filter in the form of sum of power of two (SPT) in order to avoid the multipliers during design process. The performance of the designed low-pass filter has been studied thoroughly in terms of its frequency characteristics and primitive requirement of fundamental hardware blocks. The superiority of our design has been ascertained over a number of existing techniques by various means. Finally, the proposed filter of different lengths has been implemented on a field programmable gate array (FPGA) chip for evaluating the competency of this work. The percentage improvement in hardware complexity produced by our design has also been computed and clearly listed in this paper for convenience.

Design and Factorization of Two-Channel Perfect Reconstruction Filter Banks with Causal-Stable IIR Filters

In this paper, new design and factorization methods of two-channel perfect reconstruction (PR) filter banks (FBs) with casual-stable IIR filters are introduced. The polyphase components of the analysis filters are assumed to have an identical denominator in order to simplify the PR condition. A modified model reduction is employed to derive a nearly PR causal-stable IIR FB as the initial guess to obtain a PR IIR FB from a PR FIR FB. To obtain high quality PR FIR FBs for carrying out model reduction, cosine-rolloff FIR filters are used as the initial guess to a nonlinear optimization software for solving to the PR solution. A factorization based on the lifting scheme is proposed to convert the IIR FB so obtained to a structurally PR system. The arithmetic complexity of this FB, after factorization, can be reduced asymptotically by a factor of two. Multiplier-less IIR FB can be obtained by replacing the lifting coefficients with the canonical signal digitals (CSD) or sum of powers of two (SOPOT) coefficients.

Design and Multiplierless Realization of Digital Synthesis Filters for Hybrid-Filter-Bank A/D Converters

This paper studies the optimal least squares and minimax design and realization of digital synthesis filters for hybrid-filter-bank analog-to-digital converters (HFB ADCs) to meet a given spurious-free dynamic range (SFDR). The problem for designing finite-impulse-response synthesis filters is formulated as a second-order cone-programming problem, which is convex and allows linear and quadratic constraints such as peak aliasing error to be incorporated. The fixed coefficients of the designed synthesis filters are efficiently implemented using sum-of-power-of-two (SOPOT) coefficients, while the internal word length used for each intermediate data is minimized using geometric programming. The main sources of error are analyzed, and a new formula of SFDR in terms of these errors is derived. The effects of component variations of analog analysis filters on the HFB ADC are also addressed by means of two new robust HFB ADC design algorithms based on stochastic uncertainty and worst case uncertainty models. Design results show that the proposed approach offers more flexibility and better performance than conventional methods in achieving a given SFDR and that the robust design algorithms are more robust to parameter uncertainties than the nominal design in which the uncertainties are not taken into account.

A joint encoder–decoder framework for supporting energy efficient audio decoding

In comparison with the relatively slow progress of battery technology, semiconductor memory has improved much more rapidly, making storage a less critical limiting factor in designing low power embedded systems such as PDAs. To exploit such technology trends, we present a novel framework, a joint encoder–decoder framework (JEDF), which allows the decoder to tradeoff energy and memory consumption without sacrificing playback quality. We employ sum-of-powers-of-two (SOPOT) technique, an approximate signal processing (ASP) technique, in an MPEG AAC decoder to reduce the computational workload. The SOPOT introduces additional ASP noise (in the decoder) on top of the quantization noise introduced in the process of lossy compression (in the encoder). The sum of these two kinds of noise may become audible when it exceeds the masking threshold. We tackle this problem from a new perspective: the proposed JEDF allows the ASP and quantization noises to be shaped jointly to match the masking threshold. In the case that the perceptual room between the masking threshold and the quantization noise is insufficient for the ASP noise, the JEDF can reduce the quantization noise level which results in an increase in bitrate. To implement the proposed scheme, we have developed two new techniques: (1) SOPOT truncation noise shaping; (2) truncation noise allocation based on a perceptual model. Experimental results show the effectiveness of our approach.

Design and Complexity Optimization of a New Digital IF for Software Radio Receivers With Prescribed Output Accuracy

This paper studies the design, signal round-off noise, and complexity optimization of a new digital intermediate frequency (IF) architecture for a software radio receiver (SRR). The IF under study consists of digital filters with fixed coefficients, except for a limited number of multipliers required in the Farrow-based sampling rate converter (SRC). The fixed-coefficient filters can be implemented efficiently using sum-of-power-of-two (SOPOT) coefficients and the multiplier-block technique, which gives minimum adder realization. Apart from the multipliers required in the SRC, the digital IF can be implemented without any multiplications. While most multiplier- less filter design and realization methods address only the coefficient round-off problem by minimizing the number of SOPOT terms used, the proposed design methodology aims to minimize more realistic hardware complexity measure, such as adder cells and registers, of the digital IF subject to a given spectral and accuracy specifications. The motivation is that the complexity is closely related to the target output accuracy, which is specified statistically by its total output noise power generated by rounding the intermediate data. Two novel algorithms for optimizing the internal wordlengths of linear time-invariant systems are proposed. The first one relaxes the solution to real valued and formulates the design problem as a constrained optimization. A closed-form solution can be determined by the Lagrange multiplier method. The second one is based on a discrete optimization method called the Marginal Analysis method, and it yields the desired wordlengths in integer values. Both approaches are found to be effective and suitable to large scale systems. A design example and the field programmable gate array (FPGA) realization of a multi-standard receiver are given to demonstrate the proposed method

Error Analysis and Efficient Realization of the Multiplier-Less FFT-Like Transformation (ML-FFT) and Related Sinusoidal Transformations

This paper studies the round-off analysis, design and implementation, and applications of the multiplier-less Fast Fourier Transform-like (ML-FFT) transformation proposed by Chan et al. [1, 2]. The ML-FFT parameterizes the twiddle factors in the conventional FFT algorithm as certain rotation-like matrices and approximates the associated parameters inside these matrices by the sum-of-power-of-two (SOPOT) or canonical signed digits representations, hence avoiding expensive multiplications. The error due to the SOPOT approximation is called the coefficient round-off error and it has been studied in [1, 2]. This paper studies the signal round-off error arising from internal rounding and develops a recursive noise model for ML-FFT. Using this model, a random search algorithm is proposed to minimize the hardware resources for realizing the ML-FFT subject to a prescribed output bit accuracy. To address the irregular structure of the ML-FFT due to the varying number of SOPOT terms used, a framework for its software implementation is also developed. The resulting algorithm has a regular implementation structure and is shown to offer a good performance similar to their floating-point counterpart. Finally, a new ML-FFT for real-valued input, called the ML-RFFT, is proposed. Because of the symmetry in the algorithm, it only requires about half the number of additions as required by the ML-FFT. Using the mappings between the DFT and the DCTs and DWTs, new ML-FFT-based transformations called ML-DCTs and ML-DWTs are derived. Design examples are given to demonstrate the usefulness of the proposed methods.

Biorthogonal Recombination Nonuniform Cosine-Modulated Filter Banks and their Multiplier-Less Realizations

This paper studies the theory, design and multiplier-less (ML) realization of a class of perfect reconstruction (PR) low-delay biorthogonal nonuniform cosine-modulated filter banks (CMFBs). It is based on a recombination (or merging) structure previously proposed by the authors. By relaxing the original CMFB and the recombination transmultiplexer (TMUX) in the recombination structure to be biorthogonal, nonuniform CMFBs with lower system delay can be obtained. This also increases the possible choices of the prototype filters to meet different design objectives. A matching condition is introduced to suppress the spurious response resulting from the mismatch in the transition bands of the two biorthogonal CMFBs. A complete factorization of biorthgonal CMFB using the lifting scheme is employed to obtain structurally PR biorthogonal nonuniform filter banks (FBs), which are robust to coefficient quantization. In addition, by approximating the lifting coefficients and the modulation matrices by the sum of powers-of-two (SOPOT) coefficients, ML realization with very low implementation complexity is obtained. Design examples and comparison are given to illustrate the effectiveness of the proposed method.