Abstract
In this paper, the principles of digital beamforming (DBF) and farrow structure are presented. Sum-of-powers-of-two (SOPOT) and cut-set retiming are used for saving the FPGA multiplier consumption and improving the running speed of farrow structure. A design example is given and the FPGA resource consumption saving is discussed also. The corresponding test results demonstrate the effectiveness of the fractional delay. With the fractional delay, it’s easy to realize wideband beam steering and digital beam forming.
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