Subthreshold Circuits Research Articles

Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor

Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor

Temperature Sensor with Buffer-Chain based Time-to-Digital Converter for Ultra-Low Voltage Operation

This paper proposes a Time-to-Digital Converter (TDC) based temperature sensor that aims to operate with an ultra-low voltage electromotive force for IoT applications with energy harvesting. Sub-threshold circuit design was exploited for the operation at ultra-low supply voltage. The proposed circuit uses the characteristics of leakage current for temperature measurement. The virtual ground node in the proposed sensor is charged up by leakage current and the charging time changes with the temperature. To measure the temperature-dependent charging time, we used a buffer-chain based TDC to achieve ultra-low voltage operation. Simulation results demonstrated that the minimum supply voltage for the proposed circuit is 0.15V. The power consumption is 407nW and sensing time is 180ns at 25℃. The measurable temperature range is from -40℃ to 85℃. The proposed circuit was designed with Renesas SOTB 65nm process. Simulation evaluation was conducted using HSPICE.

An Analytical MOS Device Model With Mismatch and Temperature Variation for Subthreshold Circuits

Subthreshold analog circuits are attractive for low-power, large-scale neuromorphic systems. However, subthreshold currents are exponentially sensitive to temperature and device mismatch, and a compact model that accounts for these effects is needed. We develop an analytical compact model with mismatch and temperature variation for subthreshold MOS devices. The model only requires an initial set of Monte Carlo (MC) simulations on individual devices for parameter extraction. Then the designer can use its parameterized analytical expressions for circuit design, instead of running repeated MC simulations on large circuits. We apply this model to a subthreshold current mirror design example. Good agreement between the developed model and Spectre simulations is achieved in a 28-nm fully-depleted silicon-on-insulator (FDSOI) process. The model is general and can also guide the design of other subthreshold circuits, such as low-power silicon neurons. It has been used to design Braindrop, the first neuromorphic chip programmed at a high level of abstraction.

Modeling and Analysis of Cu-Carbon Nanotube Composites for Sub-Threshold Interconnects

The sub-threshold regime is suited for applications requiring ultra-low power consumption with low to medium frequency (tens to hundreds of MHz) of operation. Therefore, this paper presents electrical modeling and comprehensive analysis of copper-carbon nanotube (Cu-CNT) composite interconnects for sub-threshold circuit design. At lower operating frequencies, the effective complex conductivity of Cu-CNT composites in the nanoscale is formulated by developing an analytical model. Based on the proposed equivalent single conductor model, the frequency-dependent resistance and inductance of composite interconnects are computed. Finally, the sub-threshold crosstalk effect, transfer gain, and Nyquist stability of coupled Cu-CNT composite interconnect are analyzed using <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ABCD</i> matrix approach.

Tunable Sub Threshold Logic Design Through Adaptive Feedback Equalization

An Efficient tunable subthreshold logic circuit planned by utilizing adaptive feedback equalization circuit. This circuit utilized in the Ladner Fischer adder. This circuit utilized in a successive advanced logic circuit to moderate the cycle variety impacts and lessen the prevailing spillage energy part in the subthreshold area. Feedback equalizer circuit changes the switching edge of its inverter. It depends on the output of the flip-flop in the past cycle to lessen the charging and releasing season of the flip-flop's information capacitance. Besides, the more modest info capacitance of the feedback equalizer lessens the switching season of the last door in the combinational logic block. Likewise present point by point energy-performance models of the adaptive feedback equalizer circuit.&#x0D;

Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits

The subthreshold circuit is a practical design style for the ultralow-power applications, but its timing estimation is a challenge due to the increasing local variation effects. The delay variation of adjacent gates is not independent because of input slew variation caused by the precedent gate, so their correlation effects are difficult to model and estimate. This article proposes a semi-analytical statistical delay model considering local variation for the subthreshold region, that is, the combination of analytical and simulation-based method. First, it decorrelates the slew influence between adjacent stages by dividing delay and output slew model into fast/slow input cases and dividing delay variation model into process variation and input slew variation. Then, it can be applied into multi-PVT conditions with a one-time SPICE nominal simulation by analyzing the independence of variability and relative variability of step input gate delay variance with output load capacitance and process, voltage, and temperature (PVT). Finally, experiments are carried out for different benchmarks, processes, voltages, and temperatures (BPVTs). The average errors of variance on different BPVTs are 4.8%, 3.1%, 4.0%, and 4.7%. Compared with other analytical works, the accuracies’ improvements of three metrics (variance, variability, and max delay) are $8.3\times $ , $9.6\times $ , and $2.7\times $ by the mean error at all test benchmarks. Compared with industrial method LVF, it has a comparable error in max path delay and runtime, and less three orders of magnitudes than LVF in characterization time and stored data (from TB to GB) at all test benchmarks.

Sub-threshold start-up circuit with dynamic body-biasing for boost converters in thermoelectric energy harvesting

A 260 mV start-up charge pump and oscillator applying dynamic bulk-biasing (DBB) for step-up converters in thermal energy harvesting is presented and validated through SPICE simulation. This DBB employs a dynamic substrate control circuit (DSCC) directly controlled by the pump clock. It can dynamically reduce sub-threshold leakages during off-state and increase conduction during on-state. This is necessary for thermoelectric harvesters with output voltages of $$\le $$ 300 mV. Performance of this DBB start-up circuit is compared to those of conventional reverse and forward bulk-biasing charge pumps. According to simulated results using the TSMC180 nm CMOS model, DBB reduces kick-start voltage to 225 mV. This proposed circuit has a 1.44 $$\times $$ –52 $$\times $$ better overall figure-of-merit (FOM) compared with conventional circuits at a supply voltage of 260 mV. It can generate 50 μW of maximum power with an unregulated output of 2.5 V within 171 μs from cold start-up. This overall improvement in speed, power and pumping efficiency facilitates battery-less solutions in biomedical applications for wearable/implanted micro-devices.

Recycling of unused leakage current for energy efficient multi-voltage systems

A novel method for the delivery of power to sub-threshold (sub-Vt) circuits is proposed. The unused leakage current during the idle-mode operation of super-threshold (super-Vt) circuits is used to supply current to the sub-Vt circuits. Super-Vt and sub-Vt circuits are characterized in a 45 nm CMOS technology, where the super-Vt circuits operate at 1.2 V and generate a sub-Vt voltage of 380 mV. The energy break-even point of the leakage reuse technique is analyzed both analytically and through simulation. The proposed technique is compared with two conventional methods, one that implements separate power distribution networks for the super-Vt and sub-Vt circuits (baseline) and the second that applies voltage stacking. The proposed leakage reuse technique implemented on the s27 ISCAS89 benchmark circuit reduces the average and peak power consumption to, respectively, 0.41× and 0.7× that of the baseline technique, while also reducing the peak voltage noise on the true ground node VSS and the settling time of the true ground voltage VSS to, respectively, 0.68× and 0.44× at a cost of a 1.24× increase in the FO4 delay. The leakage reuse technique implemented on the s208 ISCAS89 benchmark circuit resulted in a reduction of the peak voltage noise on the virtual ground node VGND and a reduction in the settling time of the virtual ground voltage VGND to, respectively, 0.28× and 0.23× that of the voltage stacking technique. In addition, the regulation of the sub-Vt supply voltage is evaluated for a variable workload executing on a 32-bit RISC-V core operating at 380 mV.

MOSFET threshold voltage modelling and parameters optimisation of new ion implant-based subthreshold device

ABSTRACT This paper introduces a new doping profile for devices to be used in subthreshold circuits. Results show that the optimised device with the proposed doping profile offers higher ON current in the subthreshold region. In this paper, threshold voltage modelling has been performed and a comparative analysis is presented between super-threshold and sub-threshold devices. We have also analysed the subthreshold swing characteristics of the device with the proposed doping profiles. Our analysis shows that better subthreshold swing and less threshold voltage variation can be achieved using our new doping profile.

Process‐induced variability modeling of subthreshold leakage power considering device stacking

SummaryThe dominance of leakage currents in circuit design has been impelled by steady downscaling of MOSFET into nanometer regime, and has become a significant component of total IC power dissipation. The issue is further aggravated with the inability to gauge the tolerance of process parameters around their nominal value. Consequently, the drive to improve the static power prediction has enticed accurate and reliable modeling of leakage current, specifically for ultralow power applications. In contrast to gate‐ and band‐to‐band‐tunneling leakages, subthreshold leakage exhibits high susceptibility to process variations and hence has been considered for variability modeling. Fluctuations in the device electrical and geometry parameters result in a wider distribution of subthreshold leakage current. Hence, taking into account stacking effect, an analytical variability model to estimate subthreshold leakage power in subthreshold circuits, in the presence of threshold voltage variations is proposed. Further, the impact of threshold voltage variability on subthreshold leakage power is modeled in conjunction with simultaneous variations in gate length and width. The leakage power variability is characterized by model‐generated distributions obtained using Monte Carlo analysis and validated against SPICE simulations. The proposed model is about 700 computationally faster than SPICE simulations with mean error being less than 0.19%.

Subthreshold Region based Linear Feedback Shift Register

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

TBAL: Tunnel FET-Based Adiabatic Logic for Energy-Efficient, Ultra-Low Voltage IoT Applications

A novel, tunnel field-effect transistor (TFET)-based adiabatic logic (TBAL) circuit topology has been proposed, evaluated and benchmarked with several device architectures (planar MOSFET, FinFET, and TFET) and AL implementations (efficient charge recovery logic, 2N-2N2P, positive feedback adiabatic logic) operating in the ultra-low voltage ( $0.3~\text{V}\geq V_{DD} \leq 0.6~\text{V}$ ) regime. By incorporating adiabatic logic functionality into standard combinational logic, an 80% reduction in energy/cycle was achieved. A further 80% reduction in energy/cycle was demonstrated by utilizing near broken-gap TFET devices and simultaneous scaling of supply voltage to 0.3 V, resulting in a 96% reduction in energy/cycle as compared to conventional Si CMOS. Extension of operating frequency beyond 10 MHz, coupled with sub-threshold circuit operation, shows the feasibility of TBAL for energy-efficient Internet of Things applications.

Modified Ion Implantation Based New Subthreshold Device Design &amp; Threshold Voltage Modelling for Ultra Low Power Applications

This paper introduces threshold voltage modelling of new doping profile for devices to be used in subthreshold circuit applications. The proposed scheme addresses doping variations along all dimensions of device. This new doping scheme proposes to employ Gaussian distribution of doping concentration along length of the channel with highest concentration at middle of channel.

Ultra low power DG FinFET based voltage controlled oscillator circuits

ABSTRACTVoltage-controlled oscillator (VCO) significantly influences power and performance in many analog and digital applications. In this era of portable electronics, power consumption has emerged as an important design metric. Intended subthreshold circuits have proven their ability to satisfy this demand of ultra low-power consumption of a multitude of applications such as RFID, microsensors, etc. Double-gate Fin-FET technology is a promising alternative to the CMOS technology for the subthreshold circuits because of its enhanced gate control, improved performance, scalability, and robustness. Therefore, this paper investigates the viability of DG FinFET Current Starved Voltage Controlled Oscillator (CSVCO) in the subthreshold regime. The results indicate the superior performance of DG FinFET-based CSVCO in regard to speed, PDP, EDP, and variability as compared to CMOS-based CSVCO. Seven different CSVCO configurations, viz.. SG, IG, hybrid, hybrid reverse, pignsg, psgnig and MIGFET, designed using different configurations of DG FinFET, are simulated using 32 nm FinFET Predictive Technology Model (PTM) in HSPICE at 150 mv power supply. The proposed pignsg CSVCO shows better results in terms of frequency obtained versus power expended giving least PDP of 1.25E-16J and better immunity to supply voltage and process variations compared to all other CSVCO configurations.

A robust asynchronous 16 × 16-bit subthreshold multiplier using SAPTL technique

Subthreshold circuit design has become a compelling method for ultra-low power applications. However, the severe performance degradation due to the exponentially reduced driving current, and the large variation of the circuit behavior caused by PVT variations both have significantly limited the application of the subthreshold circuits. Asynchronous sense amplifier-based pass transistor logic (SAPTL) is a promising method for mitigating these two main problems. This work optimizes the SAPTL circuit structure through integrating asynchronous handshaking signals into the SA circuit and applies it to a 16-bit subthreshold asynchronous multiplier circuit. Through using an asynchronous architecture, the performance and robustness against PVT variations of the multiplier are both improved. And replacing the circuits on the crucial path with the optimized SAPTL circuits further enhances the performance and reduces area overhead and energy consumption. Based on the simulations using Hspice in 130 nm CMOS process, the proposed asynchronous subthreshold multiplier circuit features 71% shorter statistic average worst-delay than the synchronous multiplier. And then utilizing the proposed SAPTL circuit can reduce the area by 43.3% and save 46.2% energy. Moreover, the Monte-Carlo simulation results demonstrate the promotion of the robustness of the proposed asynchronous multiplier circuit.

Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications

ABSTRACTClock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. Sub-threshold operation of devices is an excellent option to have an ultra-low power system. However, degraded performance and exacerbated variability are the major concerns of the sub-threshold circuits. Furthermore, as contradictory to the conventional super threshold circuits, the device resistance for the sub-threshold circuits is quite high compared to the interconnect resistance. This paper therefore, explores the design constraints for sub-threshold clock system. It further explores the suitability of buffered and un-buffered clock system in deep sub-threshold regime. The impact of supply voltage scaling and 3σ/µ variability for clock system is investigated in this work. An attempt to improve the slew of the clock system with un-buffered tree is made by redesigning the tapered H tree which exhibits better slew and robustness in sub-threshold regime.

Design of thermally aware ultra low power clock generator for moderate speed VLSI chip applications

ABSTRACTSub-threshold operation of devices provides a promising approach to satisfy the ultra-low power demand of handheld products. However, in this domain, the drive current exponentially depends on temperature which makes the sub-threshold circuits more prone to temperature variations. This paper proposes a scheme to improve the thermal stability of an ultra low power clock generator circuit which is vital for reliable operation of portable synchronous digital VLSI chip applications. In this work, combination of temperature monitoring circuit and control circuit has been incorporated to develop a thermally robust clock generator. A novel control strategy is developed, wherein the control voltage is adaptively altered to combat the exponential change in the clock period with the variation in temperature, without use of any passive components like resistors and capacitors. Simulation results shows that the proposed circuit gives constant clock period against a wide range of temperature variations. The proposed oscillator operates at 0.37V, consumes 1.5µW power and provides a temperature coefficient of 290ppm/°C over a temperature range from 10°C to120°C without any external trimming.

Power-Gating Sub-Threshold Source-Coupled Logic (PG-STSCL) circuits for ultra-low-power applications

The sub-threshold circuit design is regarded as a promising technique to provide considerable power reduction for ultra-low-power applications under tight energy constraints. This paper presents Power-Gating Sub-Threshold Source-Coupled Logic (PG-STSCL), which employs the fine-grain power gating at the gate level. It introduces isolation and retention circuits to ensure reliable propagation of data along a pipeline of power gated circuits, called a micro-pipeline. While the conventional STSCL circuits can considerably cut down the active power consumption, they have the drawback of continuous static current flow. To overcome this drawback, the proposed architecture shuts off the static current by utilizing the fine-grain power-gating technique. We have designed a 32-bit adder based on the proposed PG-STSCL gates in a 65 nm CMOS technology. The adder was simulated and compared to reference adders using standard CMOS gates, and conventional STSCL gates. Simulations demonstrated that the proposed gates provide a power reduction of 89.56% and 99.78% when compared to the standard CMOS and STSCL gates, respectively.

Nano Power Current Reference Circuit consisting of Sub-threshold CMOS Circuits

This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180- nm UMC CMOS technology. The proposed circuit consists of start-up, Bias-voltage, current-source sub-circuits with most of the MOSFETs operating in sub-threshold region. Simulation results shows that the circuit generates a stable reference current of 4-nA in supply voltage range 1 V- 1.8 V with line sensitivity of 0.203%/V.The temperature coefficient of the current was 7592ppm/°C at 1.8 V in the range of 0°C-100°C. The power dissipation was 380 NW at 1.8 V Supply. The proposed circuit would be suitable for use in sub-threshold –operated power-aware large-scale integration

Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold Parallel Architectures

This paper presents a design approach for improving energy-efficiency and throughput of parallel architectures in near- and subthreshold voltage circuits. The focus is to suppress leakage energy dissipation of the idle portions of circuits during active modes, which can allow us to wholly transform the throughput improvement from parallel architectures into energy savings via deep voltage scaling. We begin by investigating the efficacy of parallel and pipeline architectures in the near- and subthreshold circuits. The investigation reveals that active energy dissipation largely undermines the ability of deep voltage scaling to transform excessive throughput into energy savings. Techniques, such as power-gating switches (PGSs), can mitigate active-leakage power dissipation; however, the overhead for entering and exiting sleep modes can offset the energy savings provided by sleep mode, particularly if sleep time is fine grained for suppressing active leakage. Therefore, in this paper, we propose a PGS design technique, inspired by the so-called zigzag supercutoff CMOS, in order to optimize the overheads of mode transitions of PGS in near- and subthreshold circuits. The proposed technique enables to have circuits in sleep mode for as short as a single clock cycle with a negligible amount of energy and delay overheads. We apply our proposed design to parallel multiplier-based test circuits operating at near- and subthreshold voltages. Simulations show a significant improvement in energy-efficiency over baselines at the same throughput.