A robust asynchronous 16 × 16-bit subthreshold multiplier using SAPTL technique

Abstract

Subthreshold circuit design has become a compelling method for ultra-low power applications. However, the severe performance degradation due to the exponentially reduced driving current, and the large variation of the circuit behavior caused by PVT variations both have significantly limited the application of the subthreshold circuits. Asynchronous sense amplifier-based pass transistor logic (SAPTL) is a promising method for mitigating these two main problems. This work optimizes the SAPTL circuit structure through integrating asynchronous handshaking signals into the SA circuit and applies it to a 16-bit subthreshold asynchronous multiplier circuit. Through using an asynchronous architecture, the performance and robustness against PVT variations of the multiplier are both improved. And replacing the circuits on the crucial path with the optimized SAPTL circuits further enhances the performance and reduces area overhead and energy consumption. Based on the simulations using Hspice in 130 nm CMOS process, the proposed asynchronous subthreshold multiplier circuit features 71% shorter statistic average worst-delay than the synchronous multiplier. And then utilizing the proposed SAPTL circuit can reduce the area by 43.3% and save 46.2% energy. Moreover, the Monte-Carlo simulation results demonstrate the promotion of the robustness of the proposed asynchronous multiplier circuit.