Sub-threshold circuit design with shrinking CMOS devices

Abstract

This paper examines the impact of technology scaling to 22 nm on sub-threshold circuit design and proposes several solutions for sub-threshold circuits in new processes. To maintain energy-efficient sub-threshold operation, we must reduce variation and suppress leakage current. To combat random variation and minimize energy for nodes below 45 nm, we show that special strategies are needed for different categories of sub-threshold circuits.