Backside Of Substrate Research Articles

Simple, low-cost technique for photolithographic self-aligned top metal contacts tonanowires and nanotubes

We propose a new simple, low-cost method for providing all-round metal contacts toone-dimensional structures such as carbon nanotubes and nanowires on a transparentsubstrate. The nanostructures are first positioned in place to bridge a electrode gap bydielectrophoresis. The electrode structure is then used as a self-aligned mask during thesubsequent photolithography through illumination from the substrate backside. This isfollowed by metallization and lift-off. Our measurements on multi-walled carbon nanotubesthus contacted show reasonable yield and good electrical contacts for the process carriedout on a glass slide as the substrate.

Novel MMIC protection technique in plasma etching process for mechanically movable RF mems antenna

AbstractIn this article, we proposed the novel monolithic microwave integrated circuit (MMIC) protection technique in plasma etching process for MMIC mounted mechanically movable RF MEMS antenna. We could eliminate the distortion of radiation pattern caused by RF feed line on antenna frame and torsional hinge as using MMIC direct mounting on antenna plate instead of using external RF power source. Silicon‐based mechanically movable RF MEMS antenna was released using DRIE process, which was performed on the backside of silicon substrate after MMIC mounting on RF MEMS antenna plate. An aluminum layer on the front side of RF MEMS antenna plays a role of etch stop layer for DRIE process. We measured the radiation pattern as rotating the moving plate along the vertical‐ and horizontal‐direction hinge mechanically. We could obtain the radiation pattern without gain reduction and distortion of radiation pattern. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 3089–3093, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23870

Patterned wafers backside thinning for 3-D Integration and multilayer stack achievement by direct wafer bonding

ABSTRACTScaling down the devices to keep increasing the integrated circuits (ICs) performance at the rate defined by Moore's [1] law becomes more and more difficult and so costly that new circuits architectures and new integration technologies are investigated. One of the most promising ways in integration technology is the vertical stacking of circuits, also called “3D Integration”. One of the challenges in this technology is the patterned substrate backside thinning. Compatibility with the whole 3D Integration process has to be guaranteed, the existing circuit has to be kept intact and the bonding interface mustn't be damaged. In this study we discuss some experimental results of wafer thinning by grinding and polishing of molecular bonded silicon wafers applied to 3D Integration [2-4]. The wafer with patterned copper interconnections are stacked by direct SiO2 bonding and thinned down on one backside. These stacks are then bonded again to one or two circuits via a deposited oxide on the thinned surface. The top bulk Si surface was thinned down again on one backside, giving a multi layers stack. This wafer level vertical assembly demonstrates the possibility to adjust the remaining Silicon thickness to small values (<15μm) and then bond the thinned surface to achieve multiple layer 3D structure.

Implementation of anti-reflection coating to enhance light out-coupling in organic light-emitting devices

We report significant enhancement of light out-coupling in organic light-emitting devices (OLEDs) by means of anti-reflection coating of magnesium fluoride (MgF 2) on the backside of glass substrate. OLEDs were fabricated by employing the green electrophosphorescent material fac tris-(2-phenylpyridine) iridium [Ir(ppy) 3 ] doped in 4,4′,8- N, N-8-dicarbazole-biphenyl (CBP) and 0.4 wt% tetrafluorotetracyano-quinodimethane (F4-TCNQ)-doped naphthylphenylbiphenyl diamine (α-NPD) as hole transport layer (HTL). Single-layer MgF 2 with the thickness of λ/4 was then vacuum deposited on the backside of glass substrate of OLED. About two-fold enhancement in luminance with anti-reflection coating of MgF 2 has been observed.

Via-hole-based vertical GaN light emitting diodes

A vertical GaN-light emitting diode (LED) has been fabricated on a sapphire substrate with periodic via holes formed by a laser drilling technique. n-contact metal which was deposited on the backside of sapphire substrate was directly connected with an Ohmic metal of n-GaN layer through the via holes. The via-hole-based vertical GaN-LED demonstrated an optical power improvement of up to 12.5% with lower forward operating voltage compared with a conventional GaN-LED. In addition, this vertical LED showed just 0.8% and 1.5% variations of optical power and operation voltage at the 500h reliability test.

Single-step fabrication of Fresnel microlens array on sapphire substrate of flip-chip gallium nitride light emitting diode by focused ion beam

A simple one-step focused ion beam milling technique was used to fabricate a Fresnel microlens array on the backside of sapphire substrate of a gallium nitride blue light emitting diode. The optical output power from the flip-chip gallium nitride blue light emitting diode is enhanced to about 1.68 times at the injection current of 20mA. The spatial light distribution from the backside of flip-chip gallium nitride blue light emitting diode with a Fresnel microlens array shows a uniform and stronger light emission.

Improved Luminance Intensity of InGaN-GaN Light-Emitting Diode by Roughening both p-GaN and Undoped-GaN Surfaces and Applying a Mirror to the Sapphire Substrate Surface

InGaN-GaN light emitting diodes (LEDs) with double roughened surfaces and silver mirror was fabricated by surface- roughening, wafer-bonding and laser lift-off technologies. It was found the light intensity of DRM-LED (with mirror between undoped-GaN/sapphire interface) was 3.05 times higher than that of the PR-LED (with only roughened p-GaN surface), and 1.45 times higher than that of the DRSM-LED (with mirror on the backside of sapphire substrate).

Predicting the dynamic response of an extreme ultraviolet reticle during exposure scanning

Extreme ultraviolet (EUV) masks are expected to experience up to 6g’s of acceleration and achieve speeds as high as 500mm∕s while mounted in the exposure tool. Therefore, it is critical that the mounting technique employed to hold the mask in position prevents the mask from slipping under these conditions. An electrostatic pin chuck must generate adequate pressure between the mask and chuck, as well as a sufficient amount of friction. To ensure the success of such a mount design, three-dimensional finite element (FE) models have been created to predict the conditions necessary to prevent mask slippage during exposure scanning. The FE modeling is used to predict the influence of the initial substrate backside surface shape on mask flatness when mounted in the chuck, as well as the effects of friction on the relative displacement between the reticle and chuck. Simulation results indicate that for typical EUV mask substrates, coefficients of friction greater than 0.2 are necessary to prevent bulk displacement of the mask during the acceleration duty cycle. Larger coefficients may be required to limit local in-plane displacements, depending upon the initial backside shape.

Robot leg motion in a planarized-SOI, two-layer poly-Si process

With the ultimate goal of creating autonomous microrobots, we developed a five-mask process that combines two polysilicon structural layers with 50-/spl mu/m-thick SOI structures and a backside substrate etch. The polysilicon layers provide three-dimensional (3-D) hinged structures, high compliance structures, and electrical wiring. The SOI structural layer yields much stronger structures and large-force actuators. This process was developed as a part of a three-chip solution for a solar-powered 10-mg silicon robot. Here, we describe the fabrication of this planarized-SOI, two-layer poly-Si process (henceforth called the SOI/poly process), basic modules in the design of robot legs in this process, and lastly, the results of fabricated robot legs. In designing the leg structures, we developed guidelines and test structures to provide a better understanding of the robot leg performance. These guidelines include understanding the relationship between the lateral etch depth to the actuator spacing and performing static friction tests of polysilicon flaps to more accurately model the frictional forces of the linkages. Last, we report on the performance of the robot legs and inchworm motors. On an 8 mm /spl times/ 3 mm robot, we have demonstrated a 1 degree-of-freedom (DOF) robot leg, 1 mm in length, which demonstrates up to 60 /spl mu/N of vertical leg force with an angular deflection of almost 30/spl deg/. A two-DOF robot leg, also 1 mm in length, operated with at least 90/spl deg/ of angular deflection, and each inchworm motor demonstrated a shuttle displacement of 400 /spl mu/m with speeds up to 6.8 mm/s. In addition to robot legs, a bidirectional inchworm motor that produces equivalent forces in both directions was also fabricated in this SOI/poly process. This motor uses an additional set of gap-closing-actuator (GCA) arrays to prebias the drive frame.

Efficiency improvement of AlGaInN LEDs advanced by ray-tracing analysis

A modified ray-tracing model is applied to analyze the dependence of external quantum efficiency and far-field radiation pattern of AlGaInN light-emitting diodes (LEDs) on various device parameters. Considerable increase (about 1.5 times) in the efficiency is predicted for LEDs with highly reflective p-contact as compared to those with the semitransparent p-contact. It is shown that the LED's efficiency degrades with the increasing of the optical loss in AlGaInN epitaxial layers as well as with increasing of the LED chip area. The ways of improving the external efficiency of large-area (and thus, powerful) LEDs are discussed including utilization of a textured (light-scattering) backside of sapphire substrate or a diffusive interface between epitaxial layers and p-contact.

Accurate determination of optical constants of textured SnO2 using low incidence angle spectroscopic ellipsometry

Accurate optical constants (n and k) of textured SnO2 films were obtained in the range of 0.85–4.6eV using spectroscopic ellipsometry. The angular dependence of the spectroscopic ellipsometer measurement was determined at incident angles 30°, 50°, and 70° from normal to the sample surface. Depolarization components due to texturing and substrate backside reflection were separately analyzed using the measurement on polished and unpolished samples. Depolarization due to substrate backside reflection was modeled accurately. By performing the measurements at a low angle of incidence (30°), where the depolarization due to texturing is at a minimum and therefore can be neglected in the optical model, one can obtain the accurate values of n and k.

Stop‐band and band‐pass characteristics in coplanar waveguides coupled to spiral resonators

AbstractCoplanar waveguide (CPW) transmission lines periodically coupled to spiral resonators (SRs) are proposed to obtain very compact band‐pass or rejection‐band structures. The devices consist of a CPW with SRs etched on the back substrate side, underneath the slots. Due to inductive coupling between the line and the spirals, signal propagation is inhibited in the vicinity of the resonant frequency, resulting in a stop‐band structure. However, by periodically loading the line with narrow wires, this behavior is switched to a band‐pass characteristic. This has been interpreted as being due to the coexistence of a negative effective permittivity and permeability in a narrow band above resonance for the composite structure. Since the dimensions of the spirals are very small in comparison to the signal wavelength at resonance, these devices are very compact and can be of interest in applications where miniaturization is mandatory. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 42: 386–388, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20312

Monolithic integration technology between microlens arrays and infrared charge coupled devices

In this paper, we develop an integration technology between Si microlens and 256(H)×256(V) element PtSi Schottky-barrier infrared charge coupled device (IR-CCD) to improve the optical responsivity of CCD sensor. The refractive microlenses with the pixel size of approximately 28×28 μm 2 is directly fabricated on the backside of CCD substrate to focus the incident irradiation onto the active area. For the integration device the fill factor is improved by a factor of 2.1. As a result, the IR-CCD image sensors operating at 77 K indicate an approximate 0.06–0.4 increase in relative optical responsivity in the spectral range of from 1 to 5 μm . CCD imaging quality with microlens has been improved comparing to that without microlens to a great extent.

Molecular beam epitaxial growth of mid-infrared InGaAsSb laser diodes on indium-free GaSb substrates

It was experimentally observed that the presence of indium solder between the backside of GaSb substrates and the molybdenum block has a significant effect on the molecular beam epitaxial (MBE) growth of antimony compounds. X-ray diffraction and photoluminescence characterization results show that material quality was substantially improved when a custom-made substrate holder with which to avoid indium solder between GaSb substrate and molybdenum block for mounting was used. Strain compensated InGaAsSb/AlGaAsSb laser diode devices were grown by MBE. A 2.82 μm emission wavelength and a 660 A/cm2 threshold current density were obtained in the pulsed mode at room temperature.

Radiation tolerance of epitaxial silicon carbide detectors for electrons and γ-rays

Particles detectors were made using semiconductor epitaxial 4H-SiC as the detection medium. The investigated detectors are formed by Schottky contact (Au) on the epitaxial layer and an ohmic contact on the backside of 4H-SiC substrates with different micropipe densities from CREE. For radiation hardness studies, the detectors have been irradiated with electrons (8.2MeV) and γ-rays (60Co source) at fluences and doses ranging from 0 to 9.48×1014e/cm2 and 40Mrad, respectively. We present experimental data on the charge collection properties by using 4.14MeV α-particles impinging on the Schottky contact. Hundred percent Charge Collection Efficiency, CCE, is demonstrated for reverse voltages higher than the one needed to have a depletion region equal to the α-particle projected range, even after the irradiation at the highest dose. By comparing measured CCE values with the outcomes of drift–diffusion simulations, values are inferred for the hole lifetime, τp, within the neutral region of the charge carrier generation layer. τp was found to decrease with increasing radiation levels, ranging from 300ns in non-irradiated detectors to 3ns in the most irradiated ones. The diffusion contribution of the minority charge carriers to CCE is pointed out.

InGaN/GaN light-emitting diodes with a reflector at the backside of sapphire substrates

Nitride-based light-emitting diodes (LEDs) with a reflector at the backside of the sapphire substrates have been demonstrated. It was found that an SiO2/TiO2 distributed-Bragg reflector (DBR) structure could reflect more downward-emitting photons than an Al-mirror layer. It was also found that the 20-mA output power was 2.76 mW, 2.65 mW, and 2.45 mW for the DBR LED, Al-reflector LED, and conventional LED, respectively. With the same 50-mA current injection, the integrated-electroluminescence (EL) intensity of a DBR LED and an Al-reflector LED was 19% and 15% larger than that observed from a conventional LED.

Reducing stress in silicon carbide epitaxial layers

A susceptor for the epitaxial growth of silicon carbide, with an up-lifted substrate holder, is investigated and compared to other susceptor designs both experimentally and by the use of computational fluid dynamics simulations. It is shown that the wafer bending due to temperature gradients is diminished in a hot-wall reactor compared to growth in a cold-wall reactor. The substrate backside growth is diminished using the up-lifted substrate holder, limiting the substrate bending due to the backside growth. Thereby the stress built into the epitaxial layers during growth is significantly reduced. Simulations indicate a lower effective C/Si ratio over the wafer, and a lower preferable growth temperature, as compared to the original susceptor design. In addition a slightly higher growth rate is achieved.

Fabrication of complete 8 in. stencil mask for electron projection lithography

We fabricated an 8 in. stencil mask having the complementary pattern of the 70 nm rule system-on-chip device. The 8 in. stencil mask was realized from the development of a mask substrate fabricated by using the sputtering method to form a scattering silicon membrane and an intermediate stopper layer. The intermediate layer material, which functions as an etching stopper, was CrNx. This material has demonstrated high performance in stencil mask fabrication, which is described in detail. The stress in the CrNx could be controlled within ±20 MPa by adjusting the deposition condition. The deposited silicon membrane stress could be easily adjusted in the range of 0–10 MPa. The etching selectivity, when the substrate backside etching was performed, was over 1000 under the low bias power. When the deep etching process was performed using SF6 and CHF3 etching gases for the mask pattern formation, the Si/CrNx etching selectivity was over 100 under the low bias power condition. The mask substrate, which is made up of a 2-μm-thick deposited silicon membrane and 0.35-μm-thick CrNx stopper layer, enabled an 8 in. stencil mask to be fabricated for use with electron projection lithography. In complementary mask split, we used “M-Split” which was developed by Selete and ISS as a pattern split software.

Compact representation of temperature and power dependence of thermal resistance in Si, Inp and GaAs substrate devices using linear models

A general model for the dependence of integrated device thermal resistance on substrate backside temperature and power dissipation for Si, InP and GaAs substrates is derived by consideration of the role of temperature dependent thermal conductivity in each of these effects. Linearization of these model components is carried out to extract computationally simple expressions that retain very close agreement to the full equations. A parameter extraction and scaling procedure is developed which allows the linearized models to be used in a practical modeling environment. The performance of extracted and scaled model parameters in predicting thermal resistance is compared to measurements for InP substrate devices, and the agreement and predictions are found to be within 5% of measurements for two geometries, for power levels to 3 mW/μm 2 and over a 165 °C substrate temperature range. The InP device model is also implemented as a subcircuit in hspice using behavioral sources, and the results confirmed with circuit simulation.

Improvement of output coupling efficiency of organic light-emitting diodes by backside substrate modification

The emission intensity of an organic light-emitting diode at normal viewing angle and the total external emission efficiency have been increased by factors of 9.6 and 3.0, respectively, by applying spherically shaped patterns to the back of the device substrate. The technique captures light previously lost to waveguiding in the substrate and, with proper choice of substrate, light previously lost to waveguiding in the organic/anode layers. A method of applying the technique using laminated films and an optical model for evaluating coupling efficiency are also presented.