Substrate Resistance Research Articles

KPC Beta-Lactamases Are Permissive to Insertions and Deletions Conferring Substrate Spectrum Modifications and Resistance to Ceftazidime-Avibactam.

To explore the mutational possibilities of insertions and deletions (indels) in the Klebsiella pneumoniae carbapenemase (KPC) beta-lactamase, we selected for ceftazidime-avibactam-resistant mutants. Of 96 screened mutants, we obtained 19 indels (2 to 15 amino acids), all located in the loops surrounding the active site. Three antibiotic susceptibility phenotypes emerged: an extended-spectrum-beta-lactamase-like phenotype, an activity restricted to ceftazidime, and a carbapenem-susceptible KPC-like phenotype. Tolerance for indels reflects the evolvability of KPC beta-lactamase, which could challenge the therapeutic management of patients.

Stable clusters array of silicon nanowires developed by top-plating technique as a high-performance gas sensor

For a gas sensor based on aligned nanowires array, effective extraction of sensing signals produced by all of nanowires is extremely crucial to harvest high response magnitude. In this work, a stable clusters array of silicon nanowires arrays (SiNWs) with a unique aggregation interconnection (AI) configuration was proposed to boost the sensing performances of the corresponding sensor. The stable AI structure was achieved by Cu2O top-plating technique via multiple spin-coating of Cu2+ and HF solution on SiNWs. The top-plating treatment produces a unique and stable clusters array of vertical SiNWs with obvious tip AI structure of nanowires in different clusters. And the as-formed AI array is proved to be highly effective as a gas sensor in achieving highly sensitive and stable response and low detection limit at room temperature. Compared with the pristine SiNWs sensor, the AI-SiNWs sensor displayed ~64-fold enhancement in response value to 1 ppm NO2, and the limit detection concentration of NO2 gas deducted by the experiment data is 5.4 ppb. The satisfactory sensing-performances can be interpreted effectively in terms of the effectiveness of the unique AI array in extraction of electronic response signal of SiNWs sensing units and reduction of substrate resistance influence from Cu2O soldering.

Analysis of depinning behavior of drop on chemically heterogeneous surface

Three types of depinning behaviors of a drop on a heterogeneous surface are numerically investigated. Depinning is found to occur due to two processes: slow- and fast-moving. A dynamic equilibrium results from competition between gravity and the capillary force in the whole drop. At the microscopic scale, based on measurement of the real-time contact angle, the local force balance in the contact line region is maintained by the unbalanced Young's force and the substrate resistance in the slow-moving stage, while the unbalanced Young's force provides the driving force for contact line motion in the fast-moving stage.

Influence of Substrate Resistivity on Porous Silicon Small-Signal RF Properties

This article provides guidelines to design porous silicon (PS) layers regarding optimization of small-signal properties in passive structures for radio frequency (RF): insertion loss and crosstalk. Results are based on high-frequency measurements on 200-mm wafers and electromagnetic simulations up to 40 GHz. Using substrate resistivity below ${1}~\Omega $ cm allows the best tradeoff with minimized PS thickness.

Tribological behavior of friction stir processed SiP/ZA40 in-situ composites

Abstract The effect of friction stir processing (FSP) at different rotation speeds (400, 630, 800, and 1000 r/min) and traverse speeds (25 and 50 mm/min) on the tribological properties of a Si particle reinforced Zn−40Al−2Cu-based in-situ composite was investigated. After preliminary optimization, 800 r/min and 25 mm/min were selected as optimum FSP parameters. According to the results, multi-pass FSP improved the tribological properties. For instance, at an applied pressure of 0.75 MPa, the wear rate and average coefficient of friction (COF) of four-pass FSPed composite were lower than those of base composite by 53% and 50%, respectively. SEM examinations of worn surfaces, wear debris, and worn subsurfaces revealed that the intensive refinement and uniform distribution of microstructural phases, especially the coarse Si particles, reduced Si particles interspacing, and elimination of casting defects were the most important factors enhancing the substrate resistance against sliding-induced deformation. This led to the formation of stable tribolayers that improved the tribological properties.

Measurements with silicon detectors at extreme neutron fluences1

Thin pad detectors made from 75 μm thick epitaxial silicon on low resistivity substrate were irradiated with reactor neutrons to fluences from 2.5× 1016 n/cm2 to 1× 1017 n/cm2. Edge-TCT measurements showed that the active detector thickness is limited to the epitaxial layer and does not extend into the low resistivity substrate even after the highest fluence. Detector current was measured under reverse and forward bias. The forward current was higher than the reverse at the same voltage but the difference gets smaller with increasing fluence. Rapid increase of current (breakdown) above ∼ 700 V under reverse bias was observed. An annealing study at 60̂C was made to 1200 minutes of accumulated annealing time. It showed that the reverse current anneals with similar time constants as measured at lower fluences. A small increase of forward current due to annealing was seen. Collected charge was measured with electrons from 90Sr source in forward and reverse bias configurations. Under reverse bias the collected charge increased linearly with bias voltage up to 6000 electrons at 2.5× 1016 n/cm2 and 3000 electrons at 1× 1017 n/cm2. Rapid increase of noise was measured above ∼ 700 V reverse bias due to breakdown resulting in worse S/N ratio. At low bias voltages slightly more charge is measured under forward bias compared to reverse. However better S/N is achieved under reverse bias. Effective trapping times were estimated from charge collection measurements under forward bias showing that at high fluences they are much longer than values extrapolated from low fluence measurements—at 1× 1017 n/cm2 a factor of 6 larger value was measured.

Test results of ATLASPIX3 — A reticle size HVCMOS pixel sensor designed for construction of multi chip modules

High voltage CMOS pixel sensors will be or are proposed to be used in several particle physics experiments for particle tracking like Mu3e experiment. ATLASPIX3 is the first full reticle size monolithic HVCMOS sensor for construction of multi-chip modules. The specifications for the use case have been taken from ATLAS pixel upgrade in fifth layer where it was a candidate for. The size of the chip is 2.0×2.1 cm2 with periphery at one side which makes the chip 3-side buttable. ATLASPIX3 has been implemented in a standard 180 nm HVCMOS process. Each pixel has an area of 150×50μm2 and contains a large charge collecting electrode implemented as deep n-well. The depleted volume around the n-well is enlarged by a high voltage bias and the usage of higher resistivity substrate. The readout electronics supports both triggered and triggerless readout with zero-suppression. ATLASPIX3 could be used for the construction of CMOS modules for particle tracking in experiments where high time resolution, high radiation tolerance, low power and low material budget are required. In the design phase, special attention has been paid to decreasing timing differences between pixels and the rate capability of the readout.

Trilobatin ameliorates insulin resistance through IRS-AKT-GLUT4 signaling pathway in C2C12 myotubes and ob/ob mice

BackgroundTrilobatin, a natural compound, has been found to exhibit anti-diabetic properties in high-fat diet (HFD) and streptozotocin (STZ) induced type 2 diabetic mice. But up to now no research has been reported on the effect of trilobatin on insulin resistance in peripheral tissues. Herein, we determined the effects of trilobatin on insulin resistance in palmitate-treated C2C12 myotubes and ob/ob mice.MethodsMale ob/ob mice (8-10 weeks) and same background C57BL/6 mice were used to evaluate the role of trilobatin on insulin resistance; protein expression and phosphorylation were measured by western blot; glucose uptake was determined a fluorescent test.Results Treatment with trilobatin prevented palmitate-induced insulin resistance by enhancing glucose uptake and the phosphorylation of insulin resistance substrate 1 (IRS1) and protein Kinase B, (PKB/AKT), recovered the translocation of GLUT4 from cytoplasm to membrane, but preincubation with LY294002, an inhibitor of PI3K, blocked the effects of trilobatin on glucose uptake and the distribution of GLUT4 in C2C12 myotubes. Furthermore, administration with trilobatin for 4 weeks significantly improved insulin resistance by decreasing fasting blood glucose and insulin in serum, enhancing the phosphorylation of IRS1 and AKT, and recovering the expression and translocation of GLUT4 in ob/ob mice.ConclusionsIRS-AKT-GLUT4 signaling pathway might be involved in trilobatin ameliorating insulin resistance in skeletal muscle of obese animal models.

Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC

The coupling capacitance and inductance of 2D and 3D integrated circuit (IC) interconnects in deep sub-micron technology has been increased due to reduced coupling distance in such a way that their magnitudes become comparable to the area and fringing capacitance of an interconnect. This leads to an increasing risk of failure due to unintentional noise and a need for accurate noise assessment. Incorrect noise estimation could either result in defects in circuit design if the design resources are understated or it will end up with a waste of overestimation resources. In this study, a crosstalk noise model for coupled RLC on-chip interconnects has been demonstrated. Subsequently, a novel time-efficient method is proposed to estimate and optimise the crosstalk noise precisely. The proposed method calculates coupling noise as well as optimises crosstalk noise, which has been validated using SPICE. Besides the estimation of crosstalk noise for 2D interconnect, this study also estimates the crosstalk noise for through-silicon-via (TSV), which is used to connect different dies vertically in a 3D IC. Under high-frequency operation, effects of signal rise time, TSV structure (height of the TSV), substrate resistivity and the guarding TSV termination on crosstalk noise have also been studied in this work.

Optical and electrical characterization of microwave power system chemical vapour deposited (MPS-CVD) graphene on Ni electroplated Cu foil at varying temperatures

Optical and electrical properties of graphene deposited on Ni electroplated Cu foil was studied by microwave power system chemical vapour deposition. Problems associated with non-uniformity using different substrates and the control of graphene properties instigated a new method for the preparation of graphene films. The growth process involved the use of Isopropanol for the formation of radicals at varying substrate temperatures and atmospheric pressure with microwave energy to form uniform solid films. Raman spectroscopy confirmed the quality of the films and designate single-layer graphene for 2D-band at low temperature while few-layer graphene for G-band at high temperature. Scanning electron microscope revealed changes in the morphology of graphene as the deposition parameters increases. The optical analysis revealed exponential decay of absorbance with spectra fringes in the visible region and transmittance of 92.8% and 93.7% which depends on the thickness uniformity of graphene. Hall Effect measurement showed n-type carrier conductivity with large positive magnetoresistance and high electrical conductivity due to the increased number of layers, low sheet resistance and high substrate temperature. The effect of varying temperature on graphene have been investigated, perhaps, low and intermediate substrate temperature yielded better optical properties while the high temperature yielded better electrical properties.

Application of substrate as ground for designing 3D on-chip dielectric resonator antenna with improved characteristics

This paper presents a simple method to design 3D on-chip antenna with improved gain and efficiency. In the proposed method, without introducing any additional metal-based ground layer, a low resistive Si substrate is used as the ground plane for a monopole fed dielectric resonator antenna (DRA). A cylindrical DRA (CDRA) made-up of Barium Titanate (BaTiO3,εr = 24) is placed on the top side of the oxide coated Si wafer and is excited under TM011 mode with a coaxial probe inserted from the bottom of the substrate using TSV (through silicon via) hole. The proposed on-chip CDRA (OC-CDRA) designed within the foot-print area of λ0/6.12 ×λ0/6.12 provides the peak radiation gain and efficiency of 1.2 dBi and 87% respectively at its resonating frequency of 3.5 GHz. Also, it shows 14% fractional bandwidth (FBW) with respect to its resonating frequency. Further, the isolation between co- and cross (×) polarization components along the maximum radiation direction of the two principle planes with ϕ = 0° and 90° are obtained as 34 dB and 39 dB respectively. Preparing the dielectric material, the proposed OC-CDRA is fabricated and the experimentally measured results show good agreement with the simulated results.

Broadband Lumped-Element Parameter Extraction Method of Two-Port 3D MEMS In-Chip Solenoid Inductors Based on a Physics-Based Equivalent Circuit Model.

Integrated 2D spiral inductors possess low inductance per unit area, which limits their application range. However, the state of investigation into the lumped-element parameter extraction method for integrated 3D in-chip multi-turn solenoid inductors, which possess higher inductance per unit area, is inadequate. This type of inductor can thus not be incorporated into fast computer-aided design (CAD)-assisted circuit design. In this study, we propose a broadband two-port physics-based equivalent circuit model for 3D microelectromechanical system (MEMS) in-chip solenoid inductors that are embedded in silicon substrates. The circuit model was composed of lumped elements with specific physical meanings and incorporated complicated parasitics resulting from eddy currents, skin effects, and proximity effects. Based on this model, we presented a lumped-element parameter extraction method using the electronic design automation software package, Agilent Advanced Design System (ADS). This method proved to be consistent with the results of two-port testing at low to self-resonant frequencies and could thus be used in CAD-assisted circuit design. The lumped element value variations were analyzed based on the physical meaning of the elements with respect to variations in structures and the substrate resistivity of inductors. This provided a novel perspective in terms of the design of integrated in-chip solenoid inductors.

Two-Layer Solder Resist Film with Low Young’s Modulus for High Reliability

Abstract In this paper, we reveal the development of a novel two-layer Solder Resist (SR) film with low young’s modulus which consists of low young’s modulus layer that possesses excellent adhesion to substrate and thermal resistance layer which is composed of resins with high thermal resistance and great toughness. This novel two-layer SR film exhibits superior resolution and crack resistance. Furthermore, the amount of warpage is extremely low. In general, the material with low young’s modulus and high elongation is caused from weak cross-link density, resulting in poor thermal resistance and delamination which occurs when mounting at high temperature. Herein, we can inhibit delamination successfully by this new two-layer structure film with superior thermal resistance. The Coefficient of Thermal Expansion (CTE) of conventional SR for FC-BGA is 35 ppm, and modulus is 4.5 GPa, whereas, this advanced two-layer SR film exhibits CTE of 66 ppm, and modulus of 2.3 GPa. In order to compare the crack resistance between conventional SR and newly developed two-layer SR film, the film was laminated on BGA substrate (substrate size is 50 mm × 50 mm), patterned by photolithography and cured, and then, 25 mm × 25 mm chip was mounted on a BGA substrate by flip-chip bonder. Conducting thermal cycle test (TCT) and observing the number of cracks after 1000 cycles of TCT. The crack occurrence frequency of the conventional SR is 65 %, whereas that of the new two-layer SR film is 4 %. We proved clearly that high CTE and low young’s modulus demonstrate overwhelmingly high crack resistance. Besides, high resolution of this newly developed two-layer film enabled the formation of SR opening (SRO) as small as 40 μm. From the above results, the newly developed two-layer SR film with low young’s modulus is beneficial for the next generation high-density package, especially for the outermost layer of FC-BGA packages and interposers that require higher reliability.

An Analytical Model for Distributed Capacitance in Up–Down Series Stacked Inductors

Up–down series stacked inductors (UDSSIs) are known to have higher self-resonant frequency (SRF) when compared to standard series stacked inductors (SSSIs). In this article, a physics-based distributed capacitance model is presented to accurately estimate the interlayer parasitic capacitance in both these configurations. Based on our analytical formulations, it is revealed that the total capacitance reduces substantially with increasing spiral turns in UDSSI, which is in turn responsible for increased SRF and inductor figure of merit (FOM). The importance of substrate resistivity and interlayer dielectric thickness in further improved inductor FOM with UDSSI configuration is also demonstrated. Prototype inductors using SSSI and UDSSI configurations are fabricated in 0.35- $\mu \text{m}$ BiCMOS technology. The measured results showed a 70% improvement in SRF with UDSSI structure while achieving inductance, quality factor, and FOM values of 31.54 nH, 12.34, and 4.4, respectively.

Strength and Deformation Properties of Low-Alloy Steel Bolts with Electroless Ni-P Coating: An Investigation of Two Thermal Routes

Low-alloy steel bolts are used in applications where high strength is needed, although they presented low corrosion resistance, limiting their application in harsh environments. Ni-P coatings could be an alternative to protect low-alloy steel bolts against corrosion. However, Ni-P coatings must be submitted to an interdiffusion post-heat treatment, which provokes severe microstructural changes in the steel substrate, lowering its strength. This research aims to investigate two new thermal routes to obtain Ni-P coatings on low-alloy steel bolts, aiming to preserve the steel substrate's resistance and deformation properties, addressing the ASTM A320/L7 requirements. The first route proposed consists of obtaining the Ni-P coating on an austempered steel substrate, instead of a quenched/tempered one. This approach resulted in less microstructural changes during the post-heat treatment, although poor impact properties were achieved. The second thermal route consists of Ni-P coating on a quenched substrate, followed by a single-step post-heat treatment aiming to temper the substrate and promote the coatings' interdiffusion at the same time. The single-step post-heat treatment performed at 600 °C for 4 h resulted in appropriated mechanical properties while assuring the creation of a proper coating/steel interdiffusion layer, showing the feasibility to use Ni-P coatings in low-alloy steel to be used in harsh environments.

Elimination of the Low Resistivity of Si Substrates in GaN HEMTs by Introducing a SiC Intermediate and a Thick Nitride Layer

We report the effect of a thick nitride layer on the high-frequency performance of AlGaN/GaN highelectron-mobility transistors (HEMTs) grown by metal oxide chemical vapor deposition (MOCVD) on a 6-inch Czochralski (Cz)-Si substrate. The thick nitride layer was grown via a 3C-SiC intermediate layer. A significantly low parasitic pad capacitance and a comparable cutoff frequency of 4.5 GHz for 2-μm gate length devices were achieved along with excellent electron transport characteristics, such as a mobility of ~2200 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V-s and a drain current density of 520 mA/mm. The extracted small-signal equivalentcircuit parameters also verified the accuracy of the measured cutoff frequency and parasitic capacitances.

Examination of hemocompatibility and corrosion resistance of electrical discharge-treated duplex stainless steel (DSS-2205) for biomedical applications

The present article focuses on the electrical discharge treatment of duplex stainless steel (DSS-2205) to enhance its biological responses and corrosion resistance. Electrical discharge machining (EDM) was executed at different spark energy levels (by varying input factors) and 18 different morphological DSS substrates were prepared according to the L18 experimental array. Further, an electrochemical potentiodynamic test was performed on the unmachined and treated surfaces to investigate the corrosion performance. Moreover, the high corrosion resistance substrates along with untreated specimen were further analyzed for the in-vitro interaction with human red blood cells. The results claimed that the surface treatment by EDM significantly enhances the corrosion resistance (< 90%) as well as the biological responses of DSS alloy. The current of 10A, on-time = 60 µs, off-time = 150 µs, machining with W-Cu electrode in deionized water was witnessed as the best set of parameters in both corrosion and hemocompatibility test. Thus, surface alteration of DSS-2205 by EDM can be believed as a promising technique for improving the corrosion resistance and biological responses that essential for biomedical applications.

Schottky barrier height inhomogeneity in 4H-SiC surface barrier detectors

Schottky barrier height of the diodes prepared on Au/Ni/4H-SiC for surface barrier detectors were studied by electrical methods of I-V and C-V measurements. Analysis of three parameters – barrier height, ideality factor and series resistance of the prepared structures showed that it was not possible to fit in the experimental curves accurately enough with an assumption of one sharp barrier height. The structures were analyzed consecutively by the methods which assumed barrier height inhomogeneity in the diodes. Two types of algorithms were used. The first one assumed that the diode patches were practically electrically independent and each one had its own series resistance. The second approach supposed one common resistance for all the diode patches. It was shown that by the assumption of independent non-interacting diode patches much better fit in experimental I-V curves was possible that was also in accordance with the fact that the diodes were prepared on highly resistive semiconductor substrates.

STUDY OF THE Ni(OH)2 ELECTROCHROMIC PROPERTIES OF FILMS DEPOSITED ON FTO GLASS WITH AN ADDITIONAL CONDUCTING LAYER

This work attempts to evaluate the influence of substrate conductivity on electrochromic and electrochemical properties of Ni(OH)2/PVA composite films, including coloration and bleaching rate. The conductivity of FTO glass was improved by depositing a silver gird with differing line densities. For deposition of the silver lines, aerosol jet printing method was used. As a result, few electrochromic films were deposited onto bare FTO glass and FTO glass with silver grid deposited onto it. In order to investigate deposited electrochromic films, the cyclic voltammetry with simultaneous recording of the optical characteristics is used. The optical characteristics of films were rather close to each other. At the same time, their electrochemical properties are different. It is found that the additional peaks observed is that of silver, which is electrochemically active in used potential window. In addition it was observed that during electrochemical cycling of Ni(OH)2/PVA deposited on substrates with silver grid, the last changed color from shiny metallic to black color. It is proposed that color changes of silver grid caused by silver transforming to Ag2O or AgO and back to metallic silver. It is found, that for small areas of electrochromic platings, substrate resistivity has a negligible effect on coloration and bleaching rates. The coloration and bleaching rates for Ni(OH)2/PVA films deposited onto the bare substrate, the substrate with a silver grid (1 cm cell size) and the substrate with a silver grid (0.5 cm cell size) were: –1.45, –1.71, –1.40 and 1.1, 0.75, 0.84 %∙s-1. It is suggested that the effect of substrate conductivity will clearly be seen when the physical sizes of substrate increase. Also it was underlined that for further experiments for effect definition of substrate resistivity on electrochromic properties inherit conductive materials should be used

The Waffle Substrate: A Novel Approach to Reducing Substrate Resistance in SiC Power Devices

Silicon carbide (SiC) is enabling the next generation of semiconductor power devices, with performance orders-of-magnitude beyond silicon. The most important power switching device is the SiC power MOSFET, whose performance is limited by three main resistance elements: the channel, drift layer, and substrate. For blocking voltages in the range of 400-900V, substrate resistance is a major limitation. Wafer thinning is currently used to reduce the substrate resistance, but this also reduces the strength of the wafers. We report on a waffle substrate technique that relies on wafer thinning and inductively coupled plasma (ICP) etching to reduce the substrate resistance below levels achievable by thinning alone, while retaining the mechanical stability of a moderately-thinned substrate. This technique can be applied to any SiC device for which substrate resistance is a limitation.