Substrate-epitaxial Interface Research Articles

Experiment and simulation on degradation and burnout mechanisms of SiC MOSFET under heavy ion irradiation

Experiments and simulation studies on 283 MeV I ion induced single event effects of silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) were carried out. When the cumulative irradiation fluence of the SiC MOSFET reached 5 × 106 ion⋅cm−2, the drain–gate channel current increased under 200 V drain voltage, the drain–gate channel current and the drain–source channel current increased under 350 V drain voltage. The device occurred single event burnout under 800 V drain voltage, resulting in a complete loss of breakdown voltage. Combined with emission microscope, scanning electron microscope and focused ion beam analysis, the device with increased drain–gate channel current and drain–source channel current was found to have drain–gate channel current leakage point and local source metal melt, and the device with single event burnout was found to have local melting of its gate, source, epitaxial layer and substrate. Combining with Monte Carlo simulation and TCAD electrothermal simulation, it was found that the initial area of single event burnout might occur at the source–gate corner or the substrate–epitaxial interface, electric field and current density both affected the lattice temperature peak. The excessive lattice temperature during the irradiation process appeared at the local source contact, which led to the drain–source channel damage. And the excessive electric field appeared in the gate oxide layer, resulting in drain–gate channel damage.

Substrate Effects in GaN-on-Silicon RF Device Technology

The influence of the semiconducting Si substrate on the performance of GaN-on-Si RF technology is reviewed. Firstly, the formation of a parasitic conduction channel at the substrate-epitaxy interface is discussed in terms of its physical mechanism and its influence on RF loss, followed by schemes to minimize this effect. Secondly, it is shown that the presence of the parallel channel serves to backbias the III-nitride epitaxial stack and lead to current collapse even on the highly-resistive Si substrates used for RF device fabrication, analogous to GaN-on-doped Si power devices. Strategies to mitigate this issue are also presented and critically compared. Thirdly, thermal generation of carriers in Si at elevated operating temperatures leading to increased substrate loss is quantified, also followed by a discussion of possible techniques to reduce its influence on RF loss.

Spatial Mapping of Local Density Variations in Two-dimensional Electron Systems Using Scanning Photoluminescence.

We have developed a scanning photoluminescence technique that can directly map out the local two-dimensional electron density with a relative accuracy of ∼2.2 × 108 cm-2. The validity of this approach is confirmed by the observation of the expected density gradient in a high-quality GaAs quantum well sample that was not rotated during the molecular beam epitaxy of its spacer layer. In addition to this global variation in electron density, we observe local density fluctuations across the sample. These random density fluctuations are also seen in samples that were continuously rotated during growth, and we attribute them to residual space charges at the substrate-epitaxy interface. This is corroborated by the fact that the average magnitude of density fluctuations is increased to ∼9 × 109 cm-2 from ∼1.2 × 109 cm-2 when the buffer layer between the substrate and the quantum well is decreased by a factor of 7. Our data provide direct evidence for local density inhomogeneities even in very high-quality two-dimensional carrier systems.

The Use of Dopants for Defect Monitoring for Silicon-Germanium Ultra-High Vaccuum Chemical Vapor Deposition

Silicon-germanium epitaxy via ultra high vacuum chemical vapor deposition has the advantage of allowing low process temperatures. Deposition processes are sensitive to substrate surface preparation and the time delay between oxide removal and epitaxial growth. A new monitoring process utilizing doped substrates and defect decoration etching is demonstrated to have controllable and unique sensitivity to interfacial contaminants. Doped substrates were prepared and subjected to various loading conditions prior to the growth of typical Si/SiGe bilayers. Two different defect etches were performed, and the defect densities counted and confirmed as originating from the substrate-epitaxy interface. The defect densities were correlated to the concentration of interfacial oxygen. The result of this study is a suggestion for a defect monitoring technique that uses already commonplace equipment and chemicals, which has a rapid turnaround, with controllable sensitivity to substrate surface contaminants.

The Use of Dopants for Defect Monitoring for Silicon-Germanium Ultra-High Vaccuum Chemical Vapor Deposition

Si and SiGe epitaxy via UHVCVD requires an extremely clean and oxide free substrate but has the advantage of allowing low temperature epitaxy (LTE). In-situ bake-off of thin native oxides is possible at high temperatures, but is not an option for low temperature epitaxy. As a result, LTE processes are sensitive to surface preparation and the duration between oxide removal and epitaxy growth. Traditional techniques for observing interfacial contamination, such as secondary ion mass spectroscopy, are not easily integrated into a fabrication line. In addition, the off-line measurements of monitor wafers cannot detect contamination soon enough before the product wafers have gone through extensive further processing. A new monitor has been developed and demonstrated for observing the contamination of the substrate and process that occurs after the pre-epitaxy cleaning steps. This novel monitor used an ion implanted substrate along with defect etches. The sensitivity of this monitor can be controlled by adjusting the implant dose allowing tailoring to specific process targets and needs. A dilute Secco wet etch and HCl chemical vapor etch were both demonstrated for decorating the dislocation defects caused by interfacial contaminants. Using TEM, these defects were confirmed as originating from the substrate-epitaxy interface. In-line and off-line defect counting systems were then used to quantify the defect density of the novel monitor. These monitors were shown to have sensitivity to defects caused by range of interfacial contaminants. The result of this newly integrated method is a fully line integrated defect monitor using already commonplace equipment and chemicals, that has a rapid turnaround, and that is broadly sensitive to substrate surface contaminants.

Study of photon extraction efficiency in <inline-formula><math altimg="none" display="inline" overflow="scroll"><mrow><mi>InGaN</mi></mrow></math></inline-formula> light-emitting diodes depending on chip structures and chip-mount schemes

The performance of InGaN LEDs in terms of photon extraction efficiency is analyzed by the Monte Carlo photon simulation method. Simulation results show that the sidewall slanting scheme, which works well for the AlInGaP or InGaN/SiC system, plays a very minimal role in InGaN/sapphire systems. In contrast to InGaN/SiC systems, a lower refractive index sapphire substrate restricts the generated photons to enter the substrate, minimizing the chances for the photons to be deflected by the slanted sidewalls of the epitaxial semiconductor layers that are usually very thin. The limited photon transmission to the sapphire substrate also degrades the photon extraction efficiency, especially in the epitaxial side down mount. One approach to exploit the photon extraction potential of the epitaxial side down mount may be to texture the substrate-epitaxy interface, by possibly growing the epitaxial layers on a sapphire substrate that is either appropriately surface textured or patterned and etched. In this case, randomized photon deflection off the textured interface directly increases the number of photons entering the sapphire substrate, from which they easily couple out of the chip, thereby improving the photon extraction efficiency drastically.

InGaN LED에서 칩 구조 및 칩마운트 구조에 따른 광추출효율에 관한 연구

InGaN LED에서 칩 구조 및 칩마운트 구조에 따른 광추출효율의 변화를 Monte Calo 기법을 이용하여 해석하였다. Simulation을 통해 얻은 중요한 결론의 하나는, InGaAlP 또는 InGaN/SiC LED의 경우에서는 달리, InGaN/sapphire LED의 경우 칩의 측 벽면 기울임 기법의 광추출효율 개선효과가 상대적으로 미미하다는 점이다. InGaN/SiC LED의 경우와는 달리, 기판으로 사용되는 sapphire의 굴절률이 상대적으로 작아서 생성된 광자들이 기판으로 넘어가는데 전반사장벽을 만나게 되어, 많은 광자들이 기판으로 넘어가지 못하고 두께가 매우 얇은 반도체 결정층에 갇히는 현상 때문이다. 동일한 현상은 epi-down 구조의 칩 마운트에서 광추출효율이 크게 개선되지 못하는 원인으로도 작용하게 된다. 광추출효율 관점에서의 epi-down 구조의 InGaN/sapphire LED가 갖고 있는 잠재력을 살리기 위한 방법의 하나는 기판-에피택시 계면을 texturing 하는 것이라고 할 수 있는데, 이 경우 생성된 광자들이 다량기판으로 넘어갈 수 있게 되어 광추출효율이 현저하게 개선된다. The performance of the InGaN LED's in terms of the photon extraction efficiency has been analyzed by the Monte Carlo photon simulation method. Simulation results show that the sidewall slanting scheme, which works well for the AlInGaP or InGaN/SiC LED, plays a very minimal role in InGaN/sapphire LED's. In contrast to InGaN/SiC LED's, the lower refractive index sapphire substrate restricts the generated photons to enter the substrate, minimizing the chances for the photons to be deflected by the slanted sidewalls of the epitaxial semiconductor layers that are usually very thin. The limited photon transmission to the sapphire substrate also degrades the. photon extraction efficiency especially in the epitaxial-side down mount. One approach to exploit the photon extraction potential of the epitaxial-side down mount may be to texture the substrate-epitaxy interface. In this case, randomized photon deflection off the textured interface directly increases the number of the photons entering the sapphire substrate, from which they easily couple out of the chip and thereby improving the photon extraction efficiency drastically.

The substrate—epitaxial interface of GaAs and InP grown by GSMBE

The substrate—epitaxial interface of GaAs and InP grown by GSMBE

Effects of etching with a mixture of HCl gas and H2 on the GaAs surface cleaning in molecular-beam epitaxy

I n situ cleaning of GaAs substrates with a HCl gas and hydrogen mixture prior to molecular-beam epitaxy has been investigated. The chemical reaction during etching was monitored using a quadrupole mass spectrometer. After etching, reflection high-energy electron diffraction patterns revealed (2×4) arsenic-stabilized surfaces and (4×2) gallium-stabilized surfaces as reconstructed structures in the gas-etched substrate surface. These structures suggest that the gas-etched substrate surface is atomically flat, resembling an epitaxial layer surface. To study the effect of gas etching, the carrier depletion layer and the residual carbon impurity around the substrate epitaxial interface were measured by capacitance-voltage carrier profiling and secondary-ion mass spectroscopy. After gas etching, the carrier depletion was greatly reduced, from 1.2×1012 to 1×1010 cm−2. The carbon impurity around the interface also decreased by one order of magnitude. We discussed the surface-cleaning mechanism using the atomic hydrogen terminating model of the GaAs surface during etching. We then applied this etching technique to in situ cleaning of semi-insulating GaAs substrates prior to the growth of selectively doped GaAs/N-AlGaAs heterostructures with very thin GaAs buffer layers.

In situ cleaning of GaAs substrates with HCl gas and hydrogen mixture prior to MBE growth

The effect of hydrogen chloride (HCl) gas and hydrogen mixture etching on GaAs surface cleaning prior to MBE growth was studied. The carrier depletion layer formed around the substrate epitaxial layer interface was reduced significantly by the gas etching. The carbon impurity concentration around the substrate epitaxial interface, measured by secondary ion mass spectroscopy (SIMS), also decreased one order of magnitude. Reduced carrier depletion and carbon impurity concentration were almost independent of the etching depth. We thus believe that the surface cleaning effect originates in the chemical reaction between the residual carbon contamination on the substrate and nascent active hydrogen produced by HCl gas decomposition. An atomically flat surface of the gas-etched GaAs substrate was observed using in situ reflection high energy electron diffraction (RHEED).

GaAs surface cleaning by thermal oxidation and sublimation in molecular-beam epitaxy

GaAs surface cleaning by thermal oxidation and sublimation prior to molecular-beam-epitaxial growth has been investigated as a means of reducing the carrier depletion at the substrate and epitaxial layer interface. The carrier depletion between the substrate and epitaxial films, measured by a C-V carrier profiling technique, was shown to decrease significantly with an increase in the thickness of the thermal oxidation. The concentration of carbon contamination near the substrate-epitaxial interface was measured using secondary ion mass spectroscopy. The carbon concentration correlated very well with the carrier depletion. Therefore, the main origin of the carrier depletion is believed to be the carbon concentration of the initial growth surface. Based on these results, the thermal oxidation and sublimation of a semi-insulating GaAs substrate was successfully applied to improve the mobility and sheet concentration of the two-dimensional electron gas in selectively doped GaAs/N-Al0.3Ga0.7As heterostructures with very thin GaAs buffer layers.

Two-dimensional X-ray scattering

A discussion of Grazing Incidence Scattering (GIS) is presented, with an emphasis on applications of the technique. This paper is an overview of what can and has been done in this new area of surface structural science. The method is contrasted to some of the currently available techniques to show why it offers unique advantages for certain classes of problems such as the crystallography of ordered overlayers, clean reconstructed surfaces and the thermodynamics of two-dimensional melting. Some recent data for Pb layers on Cu(110) are presented to indicate the type of information that this new method can obtain. Also discussed is the application of the technique to the interfacial structure of epitaxial layers focusing on in-plane strain, lattice mismatch and the abruptness of the substrate-epitaxial interface.

The effect of substrate-epitaxial interface on the capacitance-voltage characteristics of Schottky barriers formed on sputtered films of gallium arsenide: A K Kalkurni and R J Soukup, J Vac Sci Technol, 20 (3), 1982, 807–810

The effect of substrate-epitaxial interface on the capacitance-voltage characteristics of Schottky barriers formed on sputtered films of gallium arsenide: A K Kalkurni and R J Soukup, J Vac Sci Technol, 20 (3), 1982, 807–810

The effect of substrate–epitaxial interface on the capacitance–voltage characteristics of Schottky barriers formed on sputtered films of gallium arsenide

The capacitance–voltage characteristics of Schottky diodes fabricated on sputtered GaAs do not yield straight line plots on a 1/C2 vs V curve. This anomalous behavior may be due to any one of the following mechanisms: (1) defective Schottky barrier fabrication, (2) the effect of an insulating interfacial layer, (3) nonuniform donor distribution, (4) the effect of deep traps, or (5) the effect of the substrate–epitaxial interface. Only the effect of the substrate–epitaxial interface capacitance adequately explains the anomalous behavior observed. Measurements of capacitance at 1 kHz and at 1 MHz coupled with complex impedance measurements led to a small signal linear circuit model. The temperature dependence of the circuit elements identified appropriately with physical phenomena yielded information about the Schottky barrier and the barrier formed at the epitaxial layer–substrate interface. The strong temperature dependence of the low–high junction barrier capacitance is explained using this model.

Silicon molecular beam epitaxy on arsenic-implanted and laser-processed silicon

We report on the production of doped silicon layers buried under epitaxial undoped silicon layers, giving particular attention to the abruptness of the doped-undoped silicon interface. Arsenic-implanted silicon is both annealed and atomically cleaned using pulsed laser irradiation. Surface cleanliness and surface order are checked with Auger electron spectroscopy and low energy electron diffraction respectively. Molecular beam epitaxy is done with a substrate temperature between 300 and 600 °C, resulting in an epitaxial silicon layer of typically 100 nm. Rutherford backscattering plus channeling show that the arsenic concentration drops abruptly at the substrate-epitaxy interface and that the epitaxial layer is of good crystal quality.

Deep level profiles at substrate-epitaxial interfaces in gallium phosphide

The spatial distribution of several species of deep level defects have been measured in the substrate-epitaxy interface region for both liquid phase and vapour phase gallium phosphide. It is found that certain deep levels, measured by photo-ionisation, and photo-capture methods, have greatly enhanced concentrations at the interface and in the last few microns of the substrate material. This pile up of defects is particularly severe in the vapour phase epitaxial layers. The deep level profiles have been mapped in detail for substitutional oxygen and for a transition metal associated defect. A significant difference in their behaviour has been observed. For the transition metal defect, additional in-diffusion experiments have been undertaken which confirm that the interfacial region provides preferential sitting conditions which result in a concentration enhancement. This observation is important for thin layer devices where the interfacial regions form part or are close to the active device volume. The measured capture cross-sections suggest that the large concentrations in the interface region would produce high levels of recombination, and may contribute to the large recombination velocities observed at interfaces.

GaAs f.e.t.s with graded channel doping profiles

Graded-channel GaAs f.e.t.s with the carrier concentration decreasing from the substrate-epitaxial interface outwards are observed to exhibit more linear d.c. transfer characteristics, higher reverse gate breakdown voltages and lower 3rd-order intermodulation products than f.e.t.s fabricated from companion slices with uniform or flat doping profiles.