Substrate Current Characteristics Research Articles

MOSFET substrate current model including energy transport

A new MOSFET substrate current model, incorporating energy transport, is proposed. It was found that a non-steady-state electron transport effect and two effects attributed to electron pressure are essential to calculate the substrate current characteristics accurately. The predictions from the present model compare favorably with the experimental data for MOSFET's with effective channel length down to 0.45 µm.

Stress-induced double-hump substrate current in MOSFET's

Asymmetries in substrate current characteristics due to hot-electron stressing have been observed in short-channel n-MOSFET's. Due to the localized nature of trapped charges or interface traps as a result of hot-electron stressing, transistors can show single-peak or double-hump substrate current characteristics under normal- or reverse-mode measurements. Two-dimensional simulations indicate that a high lateral electric field is generated near the source when the negative charges are trapped there. This electric field is responsible for the observed double-hump substrate current and enhanced gate current injection under reverse-mode measurements for the stressed transistors.

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in ON condition and the gate and drain voltages are selected to produce maximum substrate current.

Observation of double-hump substrate current in funnel-shape transistors

n-channel transistors with a funnel-shape (FS) channel region were fabricated with thin gate oxide (21 nm) and short-channel length (1 µm) to study the effects of channel shapes on hot-electron effects. Two interesting phenomena are observed. First, the double-hump substrate current phenomenon is found when operating with wider channel close to drain side (wide-drain mode), while the narrow-drain mode shows the usual single-peak substrate current characteristics. Second, an enhanced gate current injection is found in the wide-drain mode, which is surprising as substrate current is actually lower in this mode. The finding is interesting as it suggests that floating-gate FS-tranistors with short-channel length and thin gate oxide are more efficient in programming when operating in wide-drain mode. This contradicts the previous SIMOS EPROM device that utilizes funnel-shape channel region operating in narrow-drain mode. The discrepancy is ascribed to the occurrence of double-hump effect in substrate current and associated enhanced gate current injection in FS-transistors when channel length and gate oxide are scaled down.

An optimized and reliable LDD structure for 1-µm NMOSFET based on substrate current analysis

Optimization of the n-region concentration for n-channel MOSFET's with a lightly doped drain (LDD) structure was investigated, based on an analysis of the substrate current characteristics. When a substrate current tailing is observed, which is peculiar to the LDDFET with a low-concentration n-region, a gate current is not observed, which suggests strong resistance against hot-carrier injection. This was confirmed by a bias stress test. The optimized surface concentration for the n-region ranges from 1 × 1018cm-3to 2.5 × 1018cm-3under negligible V TH shift and less than 25-percent driving capability degradation, compared to values for a conventional MOSFET.

An Optimized and Reliable LDD Structure for 1-/spl mu/m NMOSFET Based on Substrate Current Analysis

Optimization of the n/sup -/ region concentration for n-channel MOSFET's with a lightly doped drain (LDD) structure was investigated, based on an analysis of the substrate current characteristics. When a substrate current tailing is observed, which is peculiar to the LDDFET with a low-concentration n-region, a gate current is not observed, which suggests strong resistance against hot-carrier injection. This was confirmed by a bias stress test. The optimized surface concentration for the n/sup -/ region ranges from 1 x 10/sup18/ cm/sup -3/ to 2.5 X 10/sup 18/ cm/sup -3/ under negligible V/sub TH/ shift and less than 25-percent driving capability degradation, compared to values for a conventional MOSFET.

A simple method to characterize substrate current in MOSFET's

Experimental verification of substrate current characteristics is thoroughly carried out. V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> - V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSAT</inf> , instead of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> , is shown to be the driving force of all hot-electron effects. A simple relationship between substrate current and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> - V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSAT</inf> is found. This relationship provides a convenient tool to characterize the substrate current or the channel electric field, and, hence, all hot-electron effects. Measurements of I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SUB</inf> /I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> - V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSAT</inf> at two bias points and any one channel length are sufficient to fully characterize the substrate currents for all channel lengths V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> 's and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> 's for a given technology.