Subscriber Line Interface Research Articles

Structured Design of Integrated Subscriber Line Interface System and Circuit

A structured design of Subscriber Line Interface System and Circuit will be described. A high level synthesis allows extracting overall system and circuit requirements to satisfy the desired specifications, standards, and a robust implementation. For this purpose, first the output driving stage will be analyzed and then, dc, ac, and longitudinal balance feedbacks will be considered. Then based on extracted system specifications, optimum circuit design of line-driver will be described. High-level design of line-driver as the most important circuit block which is optimized for stability, accuracy, area, and power dissipation will be elaborated.

A broadband high-voltage SLIC for a splitter- and transformerless combined ADSL-Lite/POTS linecard

A monolithic broadband subscriber line interface circuit (B-SLIC) has been integrated in the smart power technology SPT170B, combining the functionality of an analog 150-V ringing SLIC with that of a line driver for ADSL-Lite data signals. Thus the B-SLIC is the key circuit for the realization of a very compact integrated voice data (IVD) central office linecard that neither needs analog filters ("POTS-splitter") nor transformers or relays. In spite of the fundamental voltage/frequency tradeoff, the B-SLIC is able to feed high dc or ring voltages to the line, while simultaneously acting as voice and data transceiver. Total harmonic distortion values are below -60 dB even for a high 25-V/sub pp//550-kHz sine wave signal into a 200 /spl Omega/ load; ADSL-signal-based multitone power ratio (MTPR) measurements also yield results better than 60 dB. Power dissipation in simultaneous voice and data operation is about 2.2 W.

A subscriber line interface circuit with a semiconstant current battery feed

A subscriber line interface circuit with a semiconstant current battery feed

A subscriber line interface circuit with a semiconstant current battery feed

A subscriber line interface circuit with a semiconstant current battery feed

Integration of a short-loop SLIC in a low-voltage submicron BiCMOS technology

This paper presents the high-voltage building blocks of a short-loop subscriber line interface circuit (SLIC), implemented in a 5 V 0.8 /spl mu/m BiCMOS technology using fully compatible high-voltage MOS transistors. The presented circuits include a 30 V class-AB line driver, a 30 V fully differential preamplifier, and a novel common-mode feedback circuit. Using a floating-current-mirror technique, the line driver features a well-controlled quiescent current of 600 /spl mu/A and is capable of delivering more than 30 mA of current into the loop. With an area of 0.34 mm/sup 2/, the line driver exhibits a bandwidth of 3.6 MHz for a 600 /spl Omega//1 nF load. The preamplifier and its common-mode feedback circuit feature a compact size (0.1 mm/sup 2/) and small power dissipation (10 mW). The circuits are ideal for the integration of a short-loop SLIC on a single chip with other low-voltage building blocks.

Novel line-test methods using a subscriber line interface circuit

Novel line-test methods using a subscriber line interface circuit

A High Voltage Line Driver for Subscriber Loop Interfaces in a Low Voltage Submicron BiCMOS Technology

This paper presents a 30 V line driver for short loop subscriber line interface circuit applications. The high voltage line drivers was implemented in a low-voltage 0.8 μm BiCMOS process using 30 V extended-drain MOS transistors, fully compatible with the low voltage technology. Using a Quasi-Current Mirror architecture for the output stage, the line driver is capable of delivering more than 30 mA current into the lines with an idle current as low as 1 mA, satisfying the short loop requirements. With less than 0.24 mm^2 area, the circuit can be easily integrated with low-voltage circuitry on a single chip.

A 150-V subscriber line interface circuit (SLIC) in a new BiCMOS/DMOS-technology

The presented IC performs the high-voltage functions of an electronic central office subscriber line interface without the need for any transformers or relays. The challenges of subscriber line interface circuit (SLIC) integration stem from the combination of conflicting requirements: low impedance line feeding in a 150-V range, current sensing with 0.2% relative accuracy, and stability up to 200 nF loads, while operating in the harsh environment of the telephone line. The newly developed BiCMOS/DMOS process 170-V smart power technology (SPT 170) together with circuit techniques that strongly emphasize the physical device properties (e.g., buffers with DMOS outputs, n-type supply voltage switch, accuracy by polyresistors) yielded a very robust 30 mm/sup 2/ SLIC. All transmission specifications are met without trimming.

Upgrading of cable line concentrators to accept ISDN subscribers

The upgrading of already installed μP-controlled Cable Line Concentrators (CLC) in order to accept N-ISDN subscribers is presented. The CLC is inserted in the Digital Transmision System (DTS) part of the ISDN subscriber access in such a way that no changes on the ISDN equipment are required. The necessary modifications of the CLC are limited to the replacement of the subscriber line interface modules and to the adaptation of the central control unit software in order to recognize and invoke specific wake-up signals. The proposed upgrading has been applied to a recently developed CLC for ISDN subscriber lines using the DTS 2B1Q.

Fully analogue LMS adaptive notch filter in BICMOS technology

A fully analogue adaptive notch filter for meter pulse applications in analogue subscriber line systems is presented. The filter is part of an integrated circuit which includes both low voltage subscriber line interface circuit- (SLIC)- and CODEC-filter functions. The effects of offset, noise, and transient behavior are investigated, and a linear model for stability analysis is derived. Fabricated in a 1 /spl mu/m BiCMOS technology this circuit uses the benefits of accurate SC-filters, low offset comparators, and linear multipliers. Due to the adaptive approach the performance of the filter is independent of process deviations and temperature effects. The filter has been designed for an attenuation of 50 dB @ 12 or 16 kHz, a dynamic range of 103 dB and a settling time of less than 5 ms.

100-V high-performance amplifiers in BCD technology for SLIC applications

The circuits described by the authors are a line driver and a sensing amplifier. They are part of a subscriber line interface circuits (SLIC) fabricated in BCD technology that operates up to 100 V. The driver requires about 500 mu A of quiescent current, can sink and source up to 100 mA, and remains stable for all possible line lengths. The sensing amplifier senses the line current to synthesize both the AC and DC line terminations. It achieves a 2-mV offset and a gain-bandwidth product of 2.5 MHz. The adopted mixed technology allows the realization of a compact single-chip SLIC.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Identifikationsverfahren für Multirate-Systeme

An identification method for multirate systems is proposed which is suitable for direct estimation of the unknown system without any numerical requirements for deconvolution. This is achieved by designing a matched model system in accordance to the multirate properties of the original system. The identification method is applied to echo cancellation in digital subscriber line interface circuits. Some experimental results are presented

A no-trimming SLIC two-chip set with coin telephone signaling facilities

A subscriber line interface circuit (SLIC) two-chip set that eliminates off-chip functional trimming and integrates coin telephone set facilities as well as BORSCHT functions is described. The LSI chip set consists of (a) a subscriber interface IC fabricated using a 320-V dielectrically isolated bipolar process with on-chip thin-film resistors and double-layer metal, and (b) a subscriber processor IC with oversampling A-D/D-A converters and a microprogrammable digital signal processor (DSP), using a 1.6- mu m CMOS process. Chip sizes are 5.5 mm*6.06 mm and 6.0 mm*5.7 mm, respectively. Using the two-chip set, an SLIC for a coin telephone set can be designed without using high-precision filter components or hybrid ICs with functional trimming. >

A switching regulator and lightning protector for a subscriber line interface circuit

Two monolithic ICs, a switching regulator and a crowbar protector circuit fabricated in a 90-V complementary bipolar technology are described. These devices enhance the performance of a basic subscriber-line interface circuit (SLIC) by extending the range to the customer so that 20-mA DC feed current can be supplied to a 2800-/spl Omega/ loop without the need for a -72-V office battery. The power dissipation of the entire SLIC subsystem is at most 1.5 W for any length of subscriber loop. All circuitry is robustly protected from foreign 60-Hz and lightning voltages.

A monolithic 70-V subscriber line interface circuit

The design of a new monolithic 70-V BIMOS line interface circuit (BLIC), developed as a direct interface to the subscriber line, is described. This is the basic analog segment of a new subscriber-line interface circuit (SLIC). The LSI chip has been designed using a 70-V BIMOS process, combining high- and low-voltage bipolar transistors (70 and 15 V) with CMOS (15-V) transistors all using the same junction depths. The LSI chip meets stringent requirements on several specifications and performs ten basic functions.

New method for connection of test bus to a line interface circuit

An arrangement for the connection of the inward test bus to subscriber line interface circuits in an electronic telephone exchange is proposed. The described solution uses significantly fewer relays or high-voltage switches than previous solutions.

High-voltage CMOS SIMOX technology and its application to a BSH-LSI

This paper describes high-voltage CMOS separation by implanted oxygen (SIMOX) technology and its application to a BSH-LSI that provides the basic functions of battery feed, supervision, and hybrid for subscriber line interface cuircuits. This technology is characterized by the existence of an electric-field-shielding (EFS) layer formed between the buried SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and the surface Si layer by oxygen implantation. The density of localized states at the Fermi level of the EFS layer has been estimated to be about 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> using the Cohen-Fritzsche-Ovshinsky model. The EFS layer reduces substrate voltage dependence of the threshold voltage and increases the drain-to-source breakdown voltage for MOSFET's. Specifically, the drain-to-source breakdown voltage has been raised to 180 V. The BSH-LSI, which is composed of high-voltage CMOS of more than 60 V and low-voltage CMOS of 15 V, has been successfully fabricated containing resistors and capacitors. Compared with a conventional bipolar BSH-LSI, the chip size and the dissipation power of the LSI have been reduced to approximately one-third and one-half, respectively.

Reliability of High-Voltage LSI's Made Using the Dielectric Isolation Process

A high-voltage subscriber-line interface large-scale integrated (LSI) circuit with high reliability is developed. To realize 350 V blocking voltage, this high-voltage LS1 is fabricated using an epitaxial passivated integrated circuit (EPIC) dielectric isolation technology and a field plate technique. Certain instabilities, such as leakage current increase and breakdown voltage decrease, has been reduced by using an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> buried layer and a field-plate structure for a low-voltage junction in the high-voltage device. This technique produces high-voltage LSI's with long-term stability and reliability of less than 20 FIT. This is confirmed by results of a 125°C, 10 000-h operating test. It is confirmed that highvoltage LSI's made by the EPIC dielectric isolation process are as highly reliable as low-voltage conventional bipolar LSI's.

A 3-/spl mu/m CMOS Digital Codec with Programmable Echo Cancellation and Gain Setting

A 3-/spl mu/m CMOS digital signal processor (DSP) performs speech signal shaping, programmable echo cancellation and gain setting functions for telephone applications. A/D and D/A conversions are performed by making use of /spl Sigma//Spl Delta/ modulators, decimator, and interpolator filter blocks. In addition, the DSP acts as a control interface between the subscriber line interface circuit (SLIC) and the line card controller, the denouncing of eight line status bits included.

A circuit for reducing on-resistance of a p-n-p-n device at low currents

This letter proposes a useful circuit which can reduce the on-resistance of a p-n-p-n device. This circuit is contrived from experimental results showing that the on-resistance decreases as the value of a resistor inserted between the gate and cathode terminals decreases. The basic operation and features of this circuit are discussed and its usefulness is verified experimentally. The p-n-p-n device having the circuit described here shows significant reduction in the on-resistance at the low forward-current region without degradation of characteristics such as gate triggering. This p-n-p-n device is useful for subscriber line interface circuits which need low on-resistance especially at low current levels.