Sub-sampling Phase Detector Research Articles

A Dual-Path Subsampling PLL With Ring VCO Phase Noise Suppression

This article presents a 2-GHz dual-path subsampling phase-locked loop (SSPLL) with ring voltage-controlled oscillator (VCO) phase noise suppression (PNS). In addition to the conventional subsampling charge pump (SSCP), a high-pass path from the subsampling phase detector (SSPD) to the low-pass filter (LPF) is implemented in the proposed SSPLL. Due to this dual-path architecture, a new in-band zero and pole are introduced into the open-loop transfer function (zero frequency is smaller than the pole frequency), which extends the open-loop unit-gain bandwidth without sacrificing the phase margin. Consequently, the phase noise contribution of the ring VCO is suppressed while the loop stability is ensured. Meanwhile, the phase noise contribution of the high-pass path is negligible compared to the reference and ring VCO’s contribution. Measurement results show that the SSPLL’s closed-loop bandwidth is extended to around 6 MHz with a reference of 20 MHz and the jitter is reduced by 1.34 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> (from 3.52 to 2.63 ps) with a maximum noise suppression of 6.5 dB at the 1.1-MHz offset. The PNS path consumes 0.16 mW and no delay line or calibration is needed, which results in a relatively high FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{PNC}}$</tex-math> </inline-formula> value of 40.5 dB.

A Low-Jitter and Low-Spur Charge-Sampling PLL

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW.

Photonic microwave synthesizer based on optically referenced sub-sampling phase-locked optoelectronic oscillator

Wideband and low phase noise microwave synthesizers are of critical significance for various applications. Phase-locked loop (PLL) based microwave synthesizers are widely used. Normally, the phase noise of the PLL based microwave synthesizer is limited by the phase noise of the reference, phase detector, frequency divider and voltage-controlled oscillator (VCO). It is challenging to achieve a pure electronic microwave synthesizer with wide frequency coverage and low phase noise, simultaneously. Here, we propose a photonic microwave synthesizer which incorporates an ultra-low phase noise fiber mode-locked laser (MLL) based reference and a wideband frequency tunable optoelectronic oscillator (OEO) based VCO in a hybrid optoelectronic sub-sampling PLL. The frequency of the OEO can be locked to the harmonics of the repetition-rate of the fiber MLL, which combines the distinct advantages of the low phase noise of MLL and the wideband frequency tuning of OEO. A sub-sampling phase detector formed by a balanced optical microwave phase detector (BOMPD) eliminates the use of RF frequency divider and maintains low residual phase noise. We attain an X- and Ku-band photonic microwave synthesizer with over an octave frequency coverage from 8 GHz to 18 GHz, frequency synthesis step of 60.74 MHz and phase noise of -80 dBc/Hz at 100 Hz offset and -100 dBc/Hz at 1 kHz offset for 10 GHz output. The characteristics of the optoelectronic sub-sampling phase detector, the phase-locking dynamics of the hybrid optoelectronic PLL, and the phase noise of the synthesized RF signals are both theoretically and experimentally investigated. The experimental results agree well with the theoretical models. Our approach is promising to achieve wideband and low phase noise microwave synthesis.

Auxiliary Feed-Forward Noise Cancellation Techniques for a Generic Type-II Ring Oscillator Phase Locked Loop

This brief presents an auxiliary feed-forward noise cancellation (AFFNC) technique that can be applied to a generic Type-II ring oscillator (RO) PLL. The AFFNC technique uses a stand alone sub-sampling phase detector (SSPD) embedded into an alignment loop to extract and cancel noise from the RO output. Along with AFFNC, which uses one reference edge for noise extraction, a Double Sampled AFFNC (DS-AFFNC) which utilizes both the rising and falling edge of the reference for noise extraction is also presented. By using both the reference edges, higher cancellation bandwidth is achieved in DS-AFFNC. The phase-domain model developed for AFFNC and DS-AFFNC show a 2.9x and 3.9x integrated jitter reduction respectively.

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector

This paper presents an area- and energy- efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output clock of a digitally controlled oscillator (DCO) for both the equalizer adaptation and clock recovery loop, the proposed adaptive equalizer is combined with the CDR by sharing its adaptation loop including a sub-sampling phase detector (SSPD) and a digital logic circuit. Consequently, the active area and power dissipation for the adaptive equalizer are reduced. Furthermore, the SEC is proposed to improve the high-frequency jitter tolerance of the CDR. The SEC detects bit errors by observing the comparator decision and corrects the errors without any data encoding or complicate circuits. The out-of-band jitter tolerance is improved by 22.6% at 100 MHz for 17.2-dB loss channel with <10−12 bit-error rate (BER) with the proposed SEC. The SEC is applicable to various receivers with compact design at a low cost. The prototype receiver consumes 23.9 mW at 14-Gb/s and occupies 0.007 mm2 in a 28-nm CMOS technology.

A 2.4–3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration

A sub-sampling phase-locked loop (SSPLL) with loop bandwidth calibration is presented. By using a sub-sampling phase detector with gain calibration and a pulse width control circuit, the loop bandwidth deviation of the SSPLL can be reduced. This SSPLL is fabricated in a 40 nm CMOS process and its core area is 0.15mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the SSPLL is 5.81mW from a supply of 1.1V. The reference frequency is 75 MHz and the output frequency range of the SSPLL is 2.4~3.0GHz. The measured rms jitter is 2.02ps at the output frequency of 3.0GHz. With the calibration, the largest loop bandwidth deviation from 3.5MHz among five samples is reduced from -71.4% to -18.5% at 3.0GHz.

A Quadrature Sub-Sampling Phase Detector for Fast-Relocked Sub-Sampling PLL Under External Interference

Conventional sub-sampling PLLs suffer from unstable problems under external interference due to potential long relock time in some cases. To solve this issue, a novel quadrature sub-sampling phase detector (QSSPD) is proposed in this brief to eliminate phase error ambiguity and compensate gain non-linearity. Hence, relock time under external interference is dramatically reduced while maintaining the low in-band noise characteristics simultaneously. Moreover, a study on the dynamics of sub-sampling PLL is carried out based on dynamic equations of the sub-sampling loop. A 2.3-2.5 GHz integer-N SSPLL has been prototyped in a 65nm CMOS process to show the superiority of the proposed QSSPD, which reduces the relock time from 16.3μs to 4.8μs and even 1.1μs compared to conventional SSPD while suffering 5.4MHz frequency interference.

A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and -256.4-dB FoM

This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of limited output voltage range of LV charge pump (CP). Four LV building blocks, including a proportional path sub-sampling CP (SSCP), an integral path SSCP, an LV sub-sampling phase detector, and an LV digitally controlled capacitor array in the LC -based voltage-controlled oscillator, are proposed to simultaneously reduce the PLL integrated jitter and the jitter variation over supply voltage variation. Fabricated in 40-nm CMOS process with a core active area of 0.24 mm2, the LVSSPLL operates at 0.65-V supply and achieves 12–16-GHz tuning range, 56.4-fs integrated jitter at 14 GHz, 7.2-mW power consumption, and −256.4-dB figure-of-merit (FoM). The measured integrated jitter variation is less than 14.5 fs within the supply voltage range from 0.62 to 0.7 V, which shows robustness over supply voltage variation.

A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor

In this brief, a multiplying delay-locked loop (MDLL) using a frequency calibrator (FC) and a voltage monitor (VM) is presented. This FC uses a delay-calibrated subsampling phase detector (SSPD) to reduce the frequency error. The VM is used to cover a wide frequency variation. This MDLL is fabricated in 40-nm CMOS technology. Its active area is 0.013 mm2, and the power consumption is 5.2 mW from a supply of 1 V. It exhibits a root-mean-square jitter of 229 fs at 2.4-GHz output and the reference spur of −54.3 dBc under a reference clock of 150 MHz.

Feedforward Phase Noise Cancellation Exploiting a Sub-Sampling Phase Detector

This brief presents a feedforward phase noise cancellation technique to reduce phase noise of the output clock signal of a phase-locked loop (PLL). It uses a sub-sampling phase detector to measure the phase noise and a variable time delay for cancellation. Both phase noise and spurs are reduced. Analytical expressions have been derived that characterize the performance of this technique and show its fundamental limitations. A sub-sampling PLL with the cancellation technique as a built-in feature is described. The feedforward technique has no stability requirements in contrast to conventional PLL architectures. The phase noise reduction bandwidth is increased to almost a third of the reference frequency—3x the maximal bandwidth for 3rd order type-II PLLs. The proposed analytical model shows a phase noise reduction of 9 dB at a frequency offset of $ {{f_{\text {ref}}/10}}$ . The total rms jitter is improved by 7.2 dB. The analytical results are verified by simulations.

A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector

A high-order cascaded phase-locked loop (PLL) architecture using a sub-sampling delay-locked loop (DLL) is proposed to break the tradeoff between the loop bandwidth and the number of integrator in the feedback loop without significantly degrading the settling time or reference spur. A clock-skew-sampling phase detector is also proposed to extend the stable detection range of the sub-sampling phase detector. Implemented in a 65-nm CMOS process, a prototype of the proposed two-stage third-order cascaded PLL measures a 4.2- $\mu \text{s}$ settling time, 1.05-ps integrated jitter, and −113-dBc/Hz in-band phase noise at a 2.1-GHz output frequency while consuming 3.84 mW at 1.2-V supply voltage and occupying a core chip area of 0.043 mm2.

A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector

Ring-oscillator (RO)-based phase-locked loops (PLLs) are very attractive for system-on-chip applications for their compactness and tuning range, but suffer from high jitter and supply noise sensitivity. This paper presents a sub-sampling phase detector (SSPD)-based feedforward noise cancellation (FFNC) technique to improve these drawbacks of the RO PLL. The FFNC scheme utilizes the already available SSPD output to perform cancellation with high sensitivity while utilizing low power and area overhead. The 2- to 2.8-GHz RO PLL proof-of-principle prototype occupies 0.022 mm2 active area in 65 nm CMOS; it achieves a 633 fs rms jitter at 2.36 GHz with 5.86 mW power consumption and an figure of merit (FOMjitter) of −236.3 dB. The cancellation reduces the jitter by $1.4\times $ , the phase noise by 10.2 dB to −123.5 dBc/Hz at 300-kHz offset, and the RO supply sensitivity by 19.5 dB for a 1 mVpp 100-kHz noise tone on the RO supply.

A 2.4-GHz 16-Phase Sub-Sampling Fractional-N PLL With Robust Soft Loop Switching

A 16-modulo fractional-N sub-sampling phase-locked loop (SSPLL) with a quadrature voltage-controlled oscillator (VCO) interpolating 16 output phases is presented in this paper. Automatic soft switching between the sub-sampling phase control loop and the frequency control loop is proposed to improve loop robustness against perturbations and interferences, achieving more stable loop dynamics for a larger range of phase errors compared with prior art SSPLL designs. A capacitive phase interpolation network is implemented for 16-phase clock generation starting from quadrature phases. The 16 phases are further utilized to achieve fractional-N operation with a sub-sampling phase detector. This passive phase interpolation at the VCO frequency introduces no extra noise or power and avoids in-band phase noise degradation for fractional-N mode. Implemented in a 130-nm CMOS technology, the SSPLL chip achieves a measured in-band phase noise of −120 dBc/Hz and a measured integrated jitter of 158 fs at 2.4 GHz, while consuming 21 mW with 16 output phases. The measured reference spur and fractional spur levels are −72 and −52 dBc, respectively.

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

A 60 GHz sub-sampling PLL implemented in 40 nm CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30 GHz after an inductively-peaked static divide-by-two. Thanks to the lower frequency of operation, the effect of non-zero sampling aperture of the switch is minimized. A dummy divider of the quadrature PLL is utilized for the sub-sampling loop to avoid extra loading in the 60 GHz path. A 53.8–63.3 GHz QVCO uses super-harmonic coupling at 120 GHz for relaxed headroom at a 0.9 V supply and achieves a free-running phase noise down to ${-}$ 94.5 dBc/Hz at 1 MHz offset. The millimeter-wave sub-sampling PLL achieves an RMS jitter, integrated from 1 kHz to 100 MHz, of 200 fs at a power consumption of 42 mW, compared to 210 fs for the PFD/CP PLL at 75 mW. Reference spurs in both modes are below ${-}$ 40 dBc.

A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference

Sub-sampling phase detectors (SSPDs) have recently been demonstrated to enable phase-locked loop (PLL) realizations with very low in-band noise. However, the PLL becomes susceptible to disturbances or interference via substrate or power supply coupling as experienced in systems on chip (SOCs), which could put the PLL out of lock. A tri-state phase-frequency detector with a dead-zone is traditionally added to act as an auxiliary frequency-locked loop (FLL) to enable the PLL to regain lock, albeit after a long delay. We propose a different solution to combine a tri-state PFD with an SSPD wherein the PLL is prevented from losing its lock while simultaneously achieving an improved in-band phase noise performance. A 2.2 GHz integer-N PLL has been prototyped in a 65 nm CMOS process to demonstrate the advantages of the proposed combined phase detector. It was experimentally verified that the PLL is more robust to disturbances than a PLL with a sub-sampling phase detector; it achieves a measured in-band phase noise of -122 dBc/Hz when operating with the proposed combined PD from a 1.1 V supply voltage.

A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing

A low-phase-noise integer-N phase-locked loop (PLL) is attractive in many applications, such as clock generation and analog-to-digital conversion. The sub-harmonically injection-locked technique [1–3], sub-sampling technique [4], and the multiplying delay-locked loop (MDLL) [5–8] can significantly improve the phase noise of an integer-N PLL. In the sub-harmonically injection-locked technique, to inject a low-frequency reference clock into a high-frequency voltage-controlled oscillator (VCO), the injection timing should be tightly controlled [2–3]. If the injection timing varies due to process variation, it may cause a large reference spur or even cause the PLL to fails to lock [3]. In [1], a sub-harmonically injection-locked PLL (SILPLL) adopts a sub-sampling phase-detector (PD) [4] to automatically align the phase between the injection pulse and a VCO. However, a sub-sampling PD has a small capture range and a low bandwidth. The high-frequency non-linear effects of a sub-sampling PD may degrade the accuracy and limit the maximum speed of a VCO. In addition, a frequency-locked loop is needed for a sub-sampling PD. In [3], a delay line is manually adjusted to achieve the correct injection timing. However, the delay line is sensitive to process variations. Thus, the injection timing should be calibrated.

Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 μm CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is <; -80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is -121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> .