Variation Of Subthreshold Slope Research Articles

An AMOLED Pixel Circuit With a Compensating Scheme for Variations in Subthreshold Slope and Threshold Voltage of Driving TFTs

This article proposes an active-matrix organic light-emitting diode (AMOLED) pixel circuit for mobile displays with high resolution to improve the image quality of the display panel. The proposed pixel circuit, which consists of six low-temperature polycrystalline silicon thin-film transistors (TFTs) and two capacitors, compensates for variations in the threshold voltage (Vth) and subthreshold slope (SS) of driving TFTs at low gray levels. Such compensations are achieved by extending the compensation time in the diode-connection scheme, resulting in a reduction in the OLED current error (OCE) of the proposed pixel circuit. In addition, the proposed pixel circuit connects two capacitors in parallel to the gate node of the driving TFT, thus increasing the total storage capacitance value in a given capacitor area in the emission phase, resulting in a reduction in voltage distortion at the gate node. Moreover, the OCEs caused by the IR drop of ELVDD and the crosstalk due to parasitic capacitances are thoroughly investigated and analyzed. The measurement results of the proposed pixel circuit show that the OCEs at the 64th and 128th gray levels are reduced from ±3.5 and ±6.5 to ±2.0 and ±0.8 LSB, respectively, by extending the compensation time from 6.5 to 195 $\mu \text{s}$ . Therefore, the proposed pixel circuit is highly suitable for mobile AMOLED displays requiring high image quality.

The influence of ZnO layer thickness on the performance and electrical bias stress instability in ZnO thin film transistors

Thin Film Transistors (TFTs) are the active elements for future large area electronic applications, in which low cost, low temperature processes and optical transparency are required. Zinc oxide (ZnO) thin film transistors (TFTs) on SiO2/n+-Si substrate are fabricated with the channel thicknesses ranging from 20 nm to 60 nm. It is found that both the performance and gate bias stress related instabilities of the ZnO TFTs fabricated were influenced by the thickness of ZnO active channel layer. The effective mobility was found to improve with increasing ZnO thickness by up to an order in magnitude within the thickness range investigated (20–60 nm). However, thinner films were found to exhibit greater stability in threshold voltage and turn-on voltage shifts with respect to both positive and negative gate bias stress. It was also observed that both the turn on voltage (Von) and the threshold voltage (VT) decrease with increasing channel thickness. Moreover, the variations in subthreshold slope (S) with ZnO thickness as well as variations in VT and Von suggest a possible dependence of trap states in the ZnO on the ZnO thickness. This is further correlated by the dependence of VT and Von instabilities with gate bias stress.

A Compensation Method for Variations in Subthreshold Slope and Threshold Voltage of Thin-Film Transistors for AMOLED Displays

In this paper, we propose a compensation method for variations in the subthreshold slope (SS) and threshold voltage (Vth) of the low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) in an attempt to improve the image quality of the active matrix organic light-emitting diode (AMOLED) displays for mobile applications. The proposed compensation method provides a uniform voltage to the OLED according to the gray level without being affected by variations in the SS and Vth of the LTPS TFTs. To verify the performance of the proposed compensation method, a test pattern, including two pixel circuits designed for 5.7-inch quadruple high-definition AMOLED display was fabricated and measured. The measurement results showed that the proposed compensation method achieved an emission current error of the pixel circuit of only ±3.1 LSB at the 255th gray level. Therefore, the proposed compensation method is very suitable for AMOLED displays requiring high image quality.

Influence of interface structure on performance of organic field effect transistors

In organic field effect transistors (OFETs), charge transport in the conducting channel and charge injection from metal electrodes into the conducting channel is highly dependent on the quality and reliability of the insulator-organic semiconductor (OSC) and electrodes-OSC interfaces respectively. In this regard, the choice of the dielectric and the metal is as important as that of OSC. In this paper, simulation is performed using organic transistor modelling software for Rubrene based OFETs with different dielectric materials and metal contacts. Further, influence of interface traps at the insulator-OSC interface and impact of charge injection barrier and density of states (DOS) at the source electrode-OSC interface on OFETs electrical characteristics is studied. In addition, surface Fermi level pinning effect and influence of the semiconductor layer thickness is also discussed. The obtained simulation data shows that the results can be further improved by introducing high dielectric material and high work function hole injecting source/drain contacts. It is found that there is a reduction in the charge carrier mobility in disordered OSC with interface traps as compared to crystalline OSC without interface traps. Variation of both threshold voltage and practical onset voltage is observed due to the Fermi level pinning. Also, increase of threshold voltage is observed when non-linear injection occurs due to injection barrier. It is observed that the reduction of OSC layer thickness results in an increase in the drain current and variation of sub threshold slope. Steeper sub-threshold slope correlates to the lower trap density that results in better switching behaviour of OFETs. This simulation clarifies a number of issues that can help in design, fabrication and characterisation of organic electronic devices.

Compact model for short-channel symmetric double-gate junctionless transistors

In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage roll-off, series resistance, drain saturation voltage, channel shortening and saturation velocity. The threshold voltage shift and subthreshold slope variation is determined through the minimum value of the potential in the channel. Only eight model parameters are used. The model is physically-based, considers the total charge in the Si layer and the operating conditions in both depletion and accumulation. Model is validated by 2D simulations in ATLAS for channel lengths from 25nm to 500nm and for doping concentrations of 5×1018 and 1×1019cm−3, as well as for Si layer thickness of 10 and 15nm, in order to guarantee normally-off operation of the transistors. The model provides an accurate continuous description of the transistor behavior in all operating regions.

고온에서 무접합 및 반전모드 MuGFET의 문턱전압 이하에서 급격히 작은 기울기 특성

In this paper, the variation of a steep subthreshold slope at elevated temperature in nanowire n-channel junctionless and inversion mode MuGFETs has been compared. It has been observed that the subthreshold slopes are increased with the increase of the operation temperature in junctionless and inversio-mode transistors. The variation of a subthreshold slope with operation temperature is more significant in junctionless transistor than inversion-mode transistor. The temperature dependence on the variation of a subthreshold slope for different fin widths shows a similar behavior regardless of fin width. From the temperature dependence on the variation of a subthreshold slope for different substrate biases, it has been observed that the variation of a subthreshold slope is less significant when the substrate bias was applied. It is worth noting that one can achieve a subthreshold slope of below 41mV/dec at elevated temperature of 400K using the junctionless MuGFETs with a positive substrate bias.

Characterization and Modeling of Hot Carrier-Induced Variability in Subthreshold Region

We developed an analytical model that is able to predict the evolution of the subthreshold slope variability associated with hot carrier (HC) stress. The model assumes that HC stress generates interface states with a Poisson distribution and that the number of HC-induced interface states increases linearly with the HC-induced subthreshold slope variation. We validate the model by means of extensive variability data sets collected on n-channel MOSFETs in 45- and 65-nm CMOS technologies. Furthermore, we investigate the correlation between the threshold voltage and the subthreshold slope fluctuations in order to fully characterize their impact on the subthreshold current variability.

Subthreshold current model of FinFETs based on analytical solution of 3-D Poisson's equation

The potential variation in the channel obtained from analytical solution of three-dimensional (3-D) Poisson's equation is used to calculate the subthreshold current and threshold voltage of fin field-effect transistors with doped and undoped channels. The accuracy of the model has been verified by the data from 3-D numerical device simulator. The variation of subthreshold slope and threshold voltage with device geometry and doping concentration in the channel has been studied.

P-4: Microcrystalline Silicon TFTs for Active Matrix Displays

Microcrystalline silicone (μ-Si:H) TFTs were fabricated using a conventional bottom gate amorphous Si (a-Si:H) process. A unique μc-Si:H deposition technique and TFT architecture was proposed to enhance the reliability of the TFTs. This three-mask TFT fabrication process is comparable with existing a-Si:H TFT process. In order to suppress nucleation at the bottom interface, a N2 plasma passivation was conducted before the deposition of the μc-Si:H. A typical transfer characteristic of the TFTs shows a low off-current with a value of less than 1 pA and a sub-threshold slope of 0.7 V/dec. DC bias stress was applied to verify the use of μc-Si:H TFTs for AMOLED displays. After 10,000 s of stress application time, the off-current was even lowered and sub-threshold slope variation was less than 5%. For AMOLED displays, OLED pixel simulation was performed. A pixel current of 13 μA was achieved with a Vdata of 10 V. After the simulation, a linear equation for the pixel current was derived. We also present the simulation tests of simple logical electronics. At last, for Active matrix Display back-plane, a row driver with no shift compensation is simulated with good results in terms of reproducibility and reliability.

Applicability of Quasi-3D and 3D MOSFET Simulations in the ‘Atomistic’ Regime

The importance of intrinsic fluctuations to the next generation of CMOS circuits has renewed interest in simplified, computationally inexpensive routes to the analysis of circuit parameters such as threshold voltage and subthreshold slope in ensembles of devices. A quasi-3D analytic approach to the statistical analysis of these parameters in 100 × 100 nm, 70 × 70 nm and 35 × 35 nm devices has been compared to the more computationally expensive full 3D simulation. The quasi-3D approach is useful in predicting variations in subthreshold slope, although its predictions become inaccurate for devices of approximately 35 × 35 nm or smaller. It is less effective in considering variations in threshold voltage, erroneously predicting a rise of the ensemble average threshold voltage and significantly exaggerating the threshold voltage variations over the ensemble.