Subthreshold Current Research Articles

Automatic characterization of three cortical neuron types reveals two distinct adaptation mechanisms

It has been established over the last 20 years that simplified spiking neuron models are capable of reproducing the variety of firing patterns that have been found in experimental preparations, including delayed spike onset, bursting, strong or weak adaptation, refractoriness, etc. All of these models belong to the family of generalized integrate-and-fire (IF) models, but vary in the way the standard leaky integrate-and-fire model is generalized. Features to upgrade the simple integrate-and-fire include spike after-currents, dynamic threshold, smooth spike initiation and linearized subthreshold currents. Important questions are then: which of these features are needed for basic cortical computation? How many levels of complexity do we have to add to account for relevant features of cortical dynamics? Is the spike-frequency adaptation mediated by moving thresholds or spike-triggered currents? To answer these question, we developed an efficient method for parameter optimization, that is able to extract some specific features of a neuron from current-clamp experiment. More precisely we are able to estimate the spike-triggered adaptation current that mediates spike-frequency adaptation and the dynamics of the action potential threshold, along with the passive properties of a neuron (i.e. membrane time constant, reverse potential). The method relies on the separation of the parameters affecting the subthreshold voltage and those affecting the firing threshold and its dynamics. We applied our method to three different neuron classes, Fast Spiking (FS) and non-Fast Spiking (nFS) interneurons and Pyramidal neurons (Pyr). The models we extracted reproduces the excitability type of FS, nFS and Pyr neurons to a remarkable degree of accuracy so that above 90 % of the predictable spikes can be predicted while the difference in subthreshold voltage prediction is less than 1.5 mV. We also find that the adaptation is mediated by different processes in different cell types: mostly by the moving threshold for the Pyr, entirely spike-triggered current for the FS, an equal mix of threshold and current for the nFS. Finally, we show that the parameters of the adaptation currents and dynamic threshold can be used for an automatic classification of the electrophysiological traces into three well-separated classes, whereas the passive parameters alone do not contain a sufficient amount of information to do so. We observe that the three neuron types have very contrasting threshold dynamics and that efficient classification can be done using only the parameters regulating the dynamics of the threshold.

Nanoscale Two-Bit/Cell NAND Silicon-Oxide-Nitride-Oxide-Silicon Memory Device with Different Tunneling Oxide Thicknesses

Nanoscale two-bit/cell NAND-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with different tunneling oxide thicknesses were designed to reduce the short channel effect and the coupling interference. The process step and the electrical characteristics of the proposed SONOS memory devices were simulated by using SUPREM-4 and MEDICI, respectively. The short channel effect in the nanoscale two-bit/cell SONOS devices was decreased than that of the conventional devices due to a larger effective channel length. The drain current at the on-state of the proposed NAND SONOS memory devices decreased than that of the conventional NAND SONOS devices due to the high channel resistivity. The I on/I off ratio of the proposed NAND SONOS memory devices was larger than that of the conventional memory devices due to the dramatic decrease in the subthreshold current of the proposed devices. The electrical characteristics of the NAND SONOS memory devices with different tunneling oxide thicknesses were better than those of the conventional NAND SONOS devices.

A Novel Approach to Reduce the Gate and Subthreshold Leakage in a Conventional SRAM BitCell Structure at DeepSub Micron CMOS Technology

In the age of scaled silicon technology to improve the functional efficiency of a CMOS design, the device geometry and device parameters are constantly scaled. The major factors of the power consumption due to continuous reduction of the oxide thickness (tOX) is the gate leakage current in both the active and standby mode of the device and other is due to scaled supply voltage, the sub-threshold leakage current. This work proposes a novel approach called as the P3 SRAM Bit-Cell Scheme for the reduction of the active and standby leakage power through the gate and sub-threshold leakage reduction in the active and standby mode of the memory operation. As the gated transistor is of minimum feature size, so the area penalty is minimum in terms of a large memory and can be compromised. To the best of my knowledge, pMOS Gated-Ground and full-supply voltage body bias for pMOS transistor along with the PP SRAM bit-cell structure is used for the first time in the memory bit -cell design to reduce the power in 45nm CMOS technology at VDD = 0.7V and 0.8V. In comparison with the Conventional and PP SRAM Bit-cells, the active power is achieved for Write Data „0‟ as 89.21% , 94.38%, and for Write Data „1‟ as 89.23%, 94.45%, respectively at VDD = 0.7V. When the VDD = 0.8V, the active power is achieved for Write Data „0‟ as 9.15%, 93.63%, and for Write Data „1‟ as 91.68%, 93.59%, respectively.

Modeling of plasma-induced damage and its impacts on parameter variations in advanced electronic devices

A comprehensive model predicting the effects of plasma-induced damage (PID) on parameter variations in advanced metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed. The model focuses on the silicon recess structure (Si loss) in the source/drain extension region formed by high-energy ion bombardment during plasma etching. The model includes the following mechanisms: (1) damaged layer formation by ion impact and penetration, (2) Si recess structure formation by a subsequent wet etch, (3) MOSFET performance degradation, and (4) MOSFET parameter variation. Based on a range theory for plasma-etch damage, the thickness of the damaged layer exhibits a power-law dependence on the energy of the ion incident on the surface of Si substrate. Assuming that the damaged layer was formed during a gate or an offset spacer etch process, the depth of Si recess (dR) is a function of the depth profile of the created defect site (ndam), the wet-etch stripping time (tw), and the energy of the incident ion. It was found that dR also showed a power-law dependence on the average ion energy E−ion estimated from applied self-dc-bias voltage for various tw. As for MOSFET performance degradation, the threshold voltage (Vth) shifted and the shift (ΔVth) increased with an increase in E−ion and a decrease in gate length. This induces an increase in subthreshold leakage current (Ioff) for MOSFET. Technology computer-aided-design simulations were performed to confirm these results. By integrating the presented PID models, parameter variations could be predicted: Using a Monte Carlo method, it was demonstrated that PID increases parameter variations such as Vth and Ioff. It also was found that the variation in E−ion induces Vth and Ioff variations, comparable to that induced by other process parameter fluctuations such as dopant fluctuation and gate length. In summary, considering the effects of PID on parameter variations is vital for designing future ultralarge-scale-integrated circuits with billions of built-in MOSFETs.

Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors

A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk current model is constructed using Ohm's law. In addition, an analytical expression for subthreshold current is derived. The proposed model is compared with simulation data, revealing good agreement. The simplicity of the model gives a fast and easy way to understand, analyze, and design DGJL transistors comprehensively.

Implementation of Delay and Power Monitoring Schemes to Reduce the Power Consumption

process technology shrinks, the adaptive leakage power compensation scheme will become more important in realizing high-performance and low-power applications. In order to minimize total active power consumption in digital circuits, one must take into account sub-threshold leakage currents that grow exponentially as technology scales. This describes to predict how dynamic power and sub-threshold power must be balanced. The exclusive supply voltage control switching makes stable operations. The threshold voltage control successfully maintains a ratio of switching to leakage current and which represents the reduced power consumption. The goal of this paper is to: i) Maintains the optimized body bias conditions. ii) Maintains the best power-delay tradeoff. The results with a 180-nm CMOS device explain that the proposed architecture causes in the successful optimization of power.

Cholinergic and glutamatergic agonists induce gamma frequency activity in dorsal subcoeruleus nucleus neurons

The dorsal subcoeruleus nucleus (SubCD) is involved in generating two signs of rapid eye movement (REM) sleep: muscle atonia and ponto-geniculo-occipital (PGO) waves. We tested the hypothesis that single cell and/or population responses of SubCD neurons are capable of generating gamma frequency activity in response to intracellular stimulation or receptor agonist activation. Whole cell patch clamp recordings (immersion chamber) and population responses (interface chamber) were conducted on 9- to 20-day-old rat brain stem slices. All SubCD neurons (n = 103) fired at gamma frequency when subjected to depolarizing steps. Two statistically distinct populations of neurons were observed, which were distinguished by their high (>80 Hz, n = 24) versus low (35-80 Hz, n = 16) initial firing frequencies. Both cell types exhibited subthreshold oscillations in the gamma range (n = 43), which may underlie the gamma band firing properties of these neurons. The subthreshold oscillations were blocked by the sodium channel blockers tetrodotoxin (TTX, n = 21) extracellularly and N-(2,6-dimethylphenylcarbamoylmethyl)triethylammonium bromide (QX-314) intracellularly (n = 5), indicating they were sodium channel dependent. Gamma frequency subthreshold oscillations were observed in response to the nonspecific cholinergic receptor agonist carbachol (CAR, n = 11, d = 1.08) and the glutamate receptor agonists N-methyl-d-aspartic acid (NMDA, n = 12, d = 1.09) and kainic acid (KA, n = 13, d = 0.96), indicating that cholinergic and glutamatergic inputs may be involved in the activation of these subthreshold currents. Gamma band activity also was observed in population responses following application of CAR (n = 4, P < 0.05), NMDA (n = 4, P < 0.05) and KA (n = 4, P < 0.05). Voltage-sensitive, sodium channel-dependent gamma band activity appears to be a part of the intrinsic membrane properties of SubCD neurons.

Are Cav1.3 pacemaker channels in chromaffin cells? Possible bias from resting cell conditions and DHP blockers usage

Mouse and rat chromaffin cells (MCCs, RCCs) fire spontaneously at rest and their activity is mainly supported by the two L-type Ca2+ channels expressed in these cells (Cav1.2 and Cav1.3). Using Cav1.3-/- KO MCCs we have shown that Cav1.3 possess all the prerequisites for carrying subthreshold currents that sustain low frequency cell firing near resting (0.5 to 2 Hz at -50 mV)1: low-threshold and steep voltage dependence of activation, slow and incomplete inactivation during pulses of several hundreds of milliseconds. Cav1.2 contributes also to pacemaking MCCs and possibly even Na+ channels may participate in the firing of a small percentage of cells. We now show that at potentials near resting (–50 mV), Cav1.3 carries equal amounts of Ca2+ current to Cav1.2 but activates at 9 mV more negative potentials. MCCs express only TTX-sensitive Nav1 channels that activate at 24 mV more positive potentials than Cav1.3 and are fully inactivating. Their blockade prevents the firing only in a small percentage of cells (13%). This suggests that the order of importance with regard to pacemaking MCCs is: Cav1.3, Cav1.2 and Nav1. The above conclusions, however, rely on the proper use of DHPs, whose blocking potency is strongly holding potential dependent. We also show that small increases of KCl concentration steadily depolarize the MCCs causing abnormally increased firing frequencies, lowered and broadened AP waveforms and an increased facility of switching “non-firing” into “firing” cells that may lead to erroneous conclusions about the role of Cav1.3 and Cav1.2 as pacemaker channels in MCCs.2

Stochastic Resonance Can Enhance Information Transmission in Neural Networks

Stochastic resonance (SR) is a noise-induced phenomenon whereby signal detection can be improved by the addition of background noise in nonlinear systems. SR can also improve the transmission of information within single neurons. Since information processing in the brain is carried out by neural networks and noise is present throughout the brain, the hypothesis that noise and coupling play an important role in the control of information processing within a population of neurons to control was tested. Using computer simulations, we investigate the effect of noise on the transmission of information in an array of neurons, known as array-enhanced SR (AESR) in an interconnected population of hippocampal neurons. A subthreshold synaptic current (signal) modeled by a filtered homogeneous Poisson process was applied to a distal position in each of the apical dendrites, while background synaptic signals (uncorrelated noise) were presented to the midpoint in the basal dendrite. The transmembrane potentials were recorded in each cell of an array of CA1 neuron models, in order to determine spike firing times and to estimate the total and noise entropies from the spike firing times. The results show that the mutual information is maximized for a specific amplitude of uncorrelated noise, implying the presence of AESR. The results also show that the maximum mutual information increases with increased numbers of neurons and the strength of connections. Moreover, the relative levels of excitation and inhibition modulate the mutual information transfer. It is concluded that uncorrelated noise can enhance information transmission of subthreshold synaptic input currents in a population of hippocampal CA1 neuron models. Therefore, endogenous neural noise could play an important role in neural tissue by modulating the transfer of information across the network.

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied–independent gate and symmetric–asymmetric options

Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.

Subthreshold Schmitt trigger using body-bias technique for ultra low power and high performance applications

Digital subthreshold logic provides extremely low power consumption since the power supplies are kept below the threshold voltage and using the small subthreshold current of MOS transistors to operate. In this paper, a body-bias technique to match the subthreshold currents of both the NMOS and PMOS transistors is explored and a Schmitt trigger circuit employing this bias technique is proposed. Extensive circuit simulations were conducted and the results were compared with standard body bias technique in terms of performance parameters. The simulation results were obtained with 0.18 μm technology parameters. The conclusion is that Schmitt trigger with this body biasing is suitable for high performance and ultra low power applications.

A two-dimensional model for the subthreshold swing of short-channel double-gate metal–oxide–semiconductor field effect transistors with a vertical Gaussian-like doping profile

An analytical two-dimensional (2D) model for the subthreshold swing of the short-channel double-gate (DG) MOSFET with a vertical Gaussian-like doping profile is presented in this paper. The 2D potential function obtained by solving the 2D Poisson’s equation by using the evanescent mode analysis has been used to formulate the subthreshold current. The concept of the effective conduction path effect of uniformly doped DG MOSFETs has been extended to the nonuniformly doped DG MOSFETs to obtain the subthreshold swing variations against doping profile parameters as well as device parameters of the present device. The results of the model show excellent matching with the numerical simulation data obtained by using the commercially available ATLASTM, a two-dimensional device simulator from SILVACO.

NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS

Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, significant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously degraded. A dynamic forward body bias technique is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits without sacrificing the data retention capability. With the new dynamic forward body bias technique, the peak ground bouncing noise is reduced by up to 91.70% as compared to the previously published sequential MTCMOS circuits in a UMC 80 nm CMOS technology. The design tradeoffs among important design metrics such as ground bouncing noise, leakage power consumption, active power consumption, data stability, and area are evaluated.

The Cytoplasmic N-Terminal Domain of DPP6K Disrupts KChiP Modulation of Kv4 Channels

Kv4 channel modulatory subunits, including the cytoplasmic Kv channel interacting proteins (KChIPs) and transmembrane dipeptidyl peptidase-like proteins (DPLPs), have variable N-terminal domains that can dramatically influence Kv4 channel function. These modulatory effects probably underlie the distinctive properties of subthreshold A-type potassium currents (ISA) in different neuron types. In this study we have characterized unique modulatory effects encoded in the N-terminus of DPP6K, a brain DPP6 isoform named for a distinctive N-terminal lysine cluster. In co-expression studies of Kv4.2+KChIP3a+DPP6 ternary channel complexes in Xenopus oocytes, DPP6K produces dramatically slower recovery from inactivation (at −100 mV: τ-1 = 84 ms (58%), τ-2 = 324 ms (42%)) when compared to DPP6S (τ = 25 ms )or DPP6a (τ = 10 ms). The slower recovery kinetics produced by DPP6K are accompanied by a hyperpolarizing shift (∼ 8 mV) in steady-state inactivation. To explore the functional determinant for these DPP6K effects, we conducted deletion analysis and point mutations on the DPP6K N-terminal domain. The results show that the unique functional effects of DPP6K are not attributable to the distinctive lysine residues but instead depend on hydrophobic residues 12-16. Alanine scanning of residues 12-16 shows that Met-12 and Val-16 are the critical residues for these modulatory effects, with substitution of both residues completely eliminating the effects of DPP6K on inactivation. To examine the mechanism for DPP6K modulation of channel inactivation, we compared the properties of Kv4.2+KChIP3a+DPP6K to Kv4.2/Δ2-40+DPP6K. Surprisingly, Kv4.2/Δ2-40+DPP6K and Kv4.2+KChIP3a+DPP6K channels recover from inactivation similarly and have similar midpoints of steady-state inactivation (∼ −70 mV), as if DPP6K blocks the normal modulatory effects of KChIP3a.

A baseband LPF for GSM, TD-SCDMA and WCDMA multi-mode transmitters

This paper describes a low-pass reconfigurable baseband filter for GSM, TD-SCDMA and WCDMA multi-mode transmitters. To comply with 3GPP emission mask and limit TX leakage at the RX band, the out-of-band noise performance is optimized. Due to the distortion caused by the subthreshold leakage current of the switches used in capacitor array, a capacitor bypass technique is proposed to improve the filter's linearity. An automatic frequency tuning circuit is adopted to compensate the cut-off frequency variation. Simulation results show that the filter achieves an in-band input-referred third-order intercept point (IIP3) of 47 dBm at 1.2-V power supply and the out-of-band noise can meet TX SAW-less requirement for WCDMA & TD-SCDMA. The baseband filter incorporates −40 to 0 dB programmable gain control that is accurately variable in 0.5 dB steps. The filter's cut-off frequency can be reconfigured for GSM/TD-SCDMA/WCDMA multi-mode transmitter. The implemented baseband filter draws 3.6 mA from a 1.2-V supply in a 0.13 μm CMOS process.

Functional gate metal-oxide-semiconductor field-effect transistors using tunnel injection/ejection of trap charges enabling self-adjustable threshold voltage for ultralow power operation

Metal-oxide-semiconductor field-effect transistors (MOSFETs) with a functional gate, which enables self-adjustment of threshold voltage (Vth), were proposed for ultralow power operation and fabricated with conventional complementary metal-oxide-semiconductor (CMOS) technology. In the on-current state of fabricated nMOSFETs, electron ejection from the charge trap layer by direct tunneling makes Vth low and increases on-current further. In the off-current state, electron injection into the charge trap layer makes Vth high and suppresses subthreshold leakage current. Although the characteristic time of electron transfer of the functional gate from on-current state to off-current state is fairly long, the logic mode operating principle has been verified with the experimental device. Reduction of tunnel oxide thickness (Tox) will reduce the time, which will lead to the practical use of the proposed device for CMOS logic application.

Characteristics of dotlike green satellite emission in GaInN light emitting diodes

An unwanted green satellite emission in blue GaInN light emitting diodes (LEDs) has been investigated under various electrical bias conditions and temperatures. The dot-shaped green satellite emission appears only under electrically biased conditions of the LED (but not under photoluminescence excitation) and contributes directly to a high subthreshold leakage current of the LED. A weak temperature dependency of the green satellite emission intensity is observed indicating that tunneling-assisted radiative recombination involving Mg acceptors is the origin of the green emission.

Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications

The growing demand for high density VLSI circuits and the exponential dependency of the leakage current on the oxide thickness is becoming a major challenge in deep-sub-micron CMOS technology. In this work, a novel Static Random Access Memory (SRAM) Cell is proposed targeting to reduce the overall power requirements, i.e., dynamic and standby power in the existing dual-bit-line architecture. The active power is reduced by reducing the supply voltage when the memory is functional and the standby power is reduced by reducing the gate and sub-threshold leakage currents when the memory is idle. This paper explored an integrated approach at the architecture and circuit level to reduce the leakage power dissipation while maintaining high performance in deep-submicron cache memories. The proposed memory bit-cell makes use of the pMOS pass transistors to lower the gate leakage currents while full-supply body-biasing scheme is used to reduce the sub-threshold leakage currents. To further reduce the leakage current, the stacking effect is used by switching off the stack transistors when the memory is ideal. In comparison to the conventional 6T SRAM bit-cell, the total leakage power is reduced by 50% while the cell is storing data ‘1’ and 46% when data ‘0’ at a very small area penalty. The total active power reduction is achieved by 89% when cell is storing data 0 or 1. The design simulation work was performed on the deep-sub-micron CMOS technology, the 45nm, at 250C with VDD of 0.7V.

Designing digital subthreshold CMOS circuits using parallel transistor stacks

A method for designing faster digital CMOS circuits operating in the subthreshold mode is proposed. Since the threshold voltage may be lower at narrower widths owing to the inverse-narrow-width effect in modern nanometre MOSFETs, the subthreshold current may be higher than expected at these narrow widths. It is shown that using only transistor widths that maximise the current-to-capacitance ratio, either individually or in parallel stacks, as appropriate, leads to faster circuits. Speed increases of up to 2.85 times have been demonstrated in ring oscillator simulations.

A two-dimensional subthreshold current model for fullydepleted strained-SOI MOSFET

An analytical model for the subthreshold current of fully depleted strained -SOI MOSFET was developed by solving the two-dimensional (2D) Poisson equation and the conventional drift-diffusion theory. Model verification was carried out using the 2D device simulator ISE. Good agreement was obtained between the model's calculations and the simulated results. By analyzing the model, the dependence of current on the strained Si layer strain, thickness and doping was studied. This subthreshold current model provides valuable reference to the FD-SSOI MOSFET design.