Sub-quarter Micron Devices Research Articles

Formation Mechanism and Crystallographic Relationship of Epitaxy Ti and Al Thin Films in Ionized Metal Plasma Deposition

Ti thin film is widely used as a diffusion barrier to impede the Al/Cu migrating to the Si substrate in the applications requiring high temperature processes such as high temperature sputtering and reflow developed for via-filling. To improve the bottom coverage without losing the excellent diffusion blockage and other electronic properties, the ionized metal plasma (IMP) deposition technique has been developed. This method has better control of the angular distribution on the substrate, and thus has been used to deposit Ti as diffusion barriers for the subquarter micron device applications. However, the formation mechanism of the epitaxy Ti thin film deposited by ionic metal plasma deposition is not clear. In this work, the epitaxy Ti thin film has been characterized by the transmission electron microscope. The mechanism of the epitaxy Ti thin film formation and also the crystallographic relationship between the Ti and Al thin films in the IMP deposition have been analyzed in detail. The results show that the lattice image of the Ti layer in the sample as deposited has a square-block-like structure with the c axis perpendicular to the interfaces. This structure has anisotropic diffusion properties that can retard the diffusion of Al across the Ti layer in the initial stage of the high temperature Al sputtering or reflow processes.

FORMATION MECHANISM AND CRYSTALLOGRAPHIC RELATIONSHIP OF EPITAXY Ti and Al THIN FILMS IN IONIZED METAL PLASMA DEPOSITION

Ti thin film is widely used as a diffusion barrier to impede the Al/Cu migrating to the Si substrate in the applications requiring high temperature processes such as high temperature sputtering and reflow developed for via-filling. To improve the bottom coverage without losing the excellent diffusion blockage and other electronic properties, the ionized metal plasma (IMP) deposition technique has been developed. This method has better control of the angular distribution on the substrate, and thus has been used to deposit Ti as diffusion barriers for the subquarter micron device applications. However, the formation mechanism of the epitaxy Ti thin film deposited by ionic metal plasma deposition is not clear. In this work, the epitaxy Ti thin film has been characterized by the transmission electron microscope. The mechanism of the epitaxy Ti thin film formation and also the crystallographic relationship between the Ti and Al thin films in the IMP deposition have been analyzed in detail. The results show that the lattice image of the Ti layer in the sample as deposited has a square-block-like structure with the c axis perpendicular to the interfaces. This structure has anisotropic diffusion properties that can retard the diffusion of Al across the Ti layer in the initial stage of the high temperature Al sputtering or reflow processes.

Integration of Chemical Vapor Deposition Aluminum and Physical Vapor Deposition Aluminum for Aluminum Plug Process of Sub-Quarter Micron Devices

A chemical vapor deposition (CVD)-physical vapor deposition (PVD) Al plug process was successfully integrated to fabricate device wafers with sub-quarter micron technology. Metalorganic CVD (MOCVD) TiN stacked on ion metal plasma (IMP) Ti was used as the underlayer of CVD Al from dimethylaluminum hydride (DMAH). Thin, conformal CVD Al film deposited at a low temperature functioned as an effective wetting layer for PVD Al reflow. If the CVD Al film is too thick, a complete via fill is not achieved. After PVD Al reflow, Al bumps were observed atop the via, which originated from the abnormal growth of the Al grain with a non-<111> direction. A two-step PVD Al process was applied for bump removal, because a thin PVD Al layer deposited at low temperature with high power acted as a seed layer for grain growth. The CVD-PVD Al plug process exhibited via resistance and electromigration resistance superior to those of the conventional W plug process.

Integrated CVD-PVD Al Plug Process for Sub-Quarter Micron Devices: Effects of Underlayer on the Via Filling and the Microstructure of the Al Film

AbstractThe integrated CVD-PVD Al plug process was successfully applied to a sub-quarter micron device for the simultaneous formation of plugs and wires. The effects of the underlayer on the via filling and the microstructure of the CVD-PVD Al films were investigated. Three types of underlayers were examined in this work: the Ti film deposited by the ionized PVD (I-PVD) method, the MOCVD TiN film stacked on the I-PVD Ti film, and the PVD Al film deposited on the I-PVD Ti film. Excellent via filling was achieved by employing the MOCVD TiN/I-PVD Ti or the PVD Al/I-PVD Ti as an underlayer. When only I-PVD Ti film was used as an underlayer, complete via filling was not obtained, because the CVD Al film sealed the top of vias. The CVD-PVD Al film deposited on the PVD Al/I-PVD Ti underlayer also showed excellent crystallographic texture of Al &lt;111&gt; and surface morphology, which is superior to those of the CVD-PVD Al film deposited on the MOCVD TiN/I-PVD Ti underlayer.

Deposition temperature effects of high density plasma chemical vapor deposition films for subquarter micron devices application

A detailed study for the high density plasma chemical vapor deposition (HDP-CVD) process was presented to prevent metal distortion issues and metal corrosion risk. The deposition temperature increased and then saturated as the film deposited, based on the correlation of wet-etch rate and deposition temperature. The stress of HDP-CVD film also trended up, but the deposition rate decreased. Lowering of the deposition temperature of HDP-CVD film was key to preventing the metal distortion. A two-step deposition recipe with 10 s Ar cooldown was developed to solve the metal distortion issue on subquarter micron devices.

Dopant profile and defect control in ion implantation by RTA with high ramp-up rate

Ion implantation has been widely used for current production and would be used in sub-quarter micron devices. However, problems such as enhanced diffusion and junction leakage current result from point defects generated by implantation. Process optimization and refinement are essential to obtain an excellent performance in those devices. In this paper, the RTA process has been optimized to minimize enhanced diffusion in shallow junction formation and to reduce junction leakage current and variation in high energy implantation. In shallow junction formation, high temperature (1100 °C), high ramp-up rate (400 °C s −1) and short-time (50 ms) RTA is effective to obtain a junction as shallow as 50 nm with low sheet resistance of 305 Ω/. In high-energy implantation, high temperature (≥ 1100 °C) and high ramp-up rate (≥200 °C s −1) RTA reduces junction leakage current and variation, when P + ions were implanted at 1 MeV with a dose of 1 × 10 14 cm −2. These results suggest the effectiveness of high temperature and high ramp-up rate RTA on the controlling of dopant profiles and defects.

Silicide Technology in Deep Submicron Regime

ABSTRACTSilicide technology using cobalt-titanium alloy has been developed for sub-quarter micron devices. Extremely flat and epitaxial CoSi2 films are successfully grown on a (100) Si substrate. Improved SALICIDE process is not influenced by native oxide on a Si surface. This technology will be very useful in deep sub-quarter micron devices.

Electron Beam Direct Writing Techniques for the Development of Sub-Quarter-Micron Devices

Novel techniques for electron beam (EB) direct writing are established for the development of sub-quarter micron devices. These techniques include 1) use of highly stable processes for positive and negative chemical amplification resists, 2) precise pattern size control by way of proximity effect correction using the pattern-area-density method, 3) a practical improvement technique for pattern size error at the exposure-field boundary, and 4) a novel alignment technique for a substrate covered with a heavy metal film. Successful fabrication of sub-quarter-micron test devices indicates that variable-shaped EB direct writing using these techniques is the best tool for research and development of advanced devices.

Influence of the nature of the mask on polysilicon gate patterning in high density plasmas

High density plasma etching processes of polysilicon gates on thin gate oxide (4.5 nm) have been studied for sub-quarter micron device fabrication. The influence of the mask material on the etching performance has been investigated using either a photoresist mask or an oxide hard mask. Trenching phenomena can be observed at the edges of the gates with both types of mask. When using a photoresist mask, severe defects are formed in the gate oxide near the polysilicon gate, showing that the gate oxide has been preferentially etched during the process. We show that these defects can be attributed to the trenching induced by the main etching step of the process, which is transferred into the gate oxide before the overetch starts. The transfer of the trenching effect depends strongly on the polysilicon-to-oxide selectivity which is shown to be dependent on the presence of carbon in the process chamber. When replacing the photoresist mask by an oxide hard mask the polysilicon-to-oxide selectivity can be improved by a factor of greater than three. Therefore, the use of an oxide hard mask results in a larger process window without creating undesirable defects in the active areas of the devices.