Submicron CMOS Process Research Articles

First generation of deep n-well CMOS MAPS with in-pixel sparsification for the ILC vertex detector

In this paper we present the characterization results relevant to a deep n-well (DNW) CMOS active pixel sensor chip designed for vertexing applications at the International Linear Collider. In this chip, named sparsified digital readout (SDR0), for the first time we implemented a sparsification logic at the pixel level. The DNW available in deep submicron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors. In this work, the experimental characterization of the SDR0 chip, including data from radioactive source ( 55 Fe ) tests, will be presented.

Design and fabrication of the suspended high-Q spiral inductors with X-beams

In this paper, deep sub-micron CMOS process compatible high Q on-chip spiral inductors with air gap structure were designed and fabricated. In the design the electromagnetic solver, SONNET, and the finite element program, ANSYS, were used for electrical-characteristics and maximum mechanical strength, respectively. The copper wires were capped with electroless Ni plating to prevent the copper from oxidizing. A Si3N4/SiO2 X-beam was designed to increase the mechanical strength of the inductor in air gap. The enhancement of maximum mechanical strength of a spiral inductor with X-beams is more than 4,500 times. Among these structures, the measured maximum quality factor (Q) of the suspending inductor and frequency at maximum Q are improved from 5.2 and 1.6 GHz of conventional spiral inductor to 7.3 and 2.1 GHz, respectively.

Recent progress in the development of a monolithic active pixel detector for a B factory

Monolithic Active Pixel Sensors (MAPS) may become the building blocks of vertex detectors at future high luminosity e + e - colliders. Requiring an active layer only a few tens of microns thick, MAPS can be thinned to ∼ 50 μ m , which reduces the multiple scattering of primary particles. Deep sub-micron CMOS processes allow for small pixel size, needed for adequate single point resolution and low occupancy at a Super B factory. Major concerns with MAPS are readout speed and signal stability for large pixel arrays. Laser bench test results of a full size prototype (CAP3) with 118,784 readout pixels and a 5-deep correlated double sampling pipeline are presented. Lessons learned are applied to a design iteration and investigation of two new digital readout sensor designs, all included in the CAP4 prototype chip.

Deep sub-micron chip development

The application of a deep sub-micron CMOS process is rapidly being proliferated under a multi-chip project service through the joint efforts of related universities and research organizations. In order to compensate for the shortage in designer resources, circuit libraries of sub-micron CMOS processes have been organized to be used by amateur designers. In practice, the libraries are employed in several projects, and, thus, the libraries themselves gradually become more sophisticated to the extent of even being utilized for very recent fabrication processes such as a deep sub-micron FD-SOI CMOS process. A test circuit for the SOI CMOS process is designed and submitted to examine its performance and usefulness in a front-end analog circuit of radiation detectors.

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

This paper describes a methodology for selecting drain current, inversion level (represented by inversion coefficient), and channel length for optimum performance tradeoffs in analog CMOS design. Here, inversion coefficient replaces width as a design choice to permit a conscious optimization of inversion level while width is implicitly considered. Transconductance, gate-referred thermal-noise voltage, and drain-source saturation voltage are optimized towards weak inversion while transconductance linearity and drain-referred thermal-noise current are optimized in strong inversion. Voltage gain, flicker noise, and dc mismatch are optimized towards weak inversion at long channel length while bandwidth is optimized in strong inversion at short channel length. Optimization expressions are given along with measured transconductance efficiency and Early voltage from weak through strong inversion over a wide range of channel lengths. Transconductance efficiency and Early voltage are used as normalized measures of transconductance and drain-source resistance, independent of drain current. The methodology presented is used to design three 0.5-?m operational transconductance amplifiers having equal 50-?A bias currents, but different tradeoffs in gain, bandwidth, noise, and dc mismatch. The amplifiers have measured voltage gains of 16.8, 110, and 326 V/V, ?3-dB bandwidths of 350, 51, and 5 MHz, input-referred flicker-noise voltage at 100 Hz of 2,000, 450, and 58 nV/Hz1/2, and input-referred dc mismatch voltages of 10.2, 2.2, and 1.1 mV respectively. The design methodology can be readily extended to deeper submicron CMOS processes.

Switched capacitor bandgap voltage reference for sub-1-V operation

A switched capacitor bandgap voltage reference circuit capable of sub-1-V operation is presented. The proposed circuit generates a sub-1-V reference voltage with a switched capacitor operation, offering several performance advantages over the current-mode sub-1-V counterpart. The proposed design provides an improved supply rejection and outperforms in the presence of process variation. In addition, the circuit does not require a start-up circuit and the associating trimming circuitry is simplistic and cost effective. The proposed sub-1-V switched capacitor BGR can be a practical sub-1-V reference candidate in ultra deep sub-micron CMOS processes.

Development of ASICs for CdTe pixel and line sensors

We are developing low noise analog ASICs for hard X-ray and gamma-ray astronomy. They are based on a sub-micron CMOS process. Our design includes a finely-adjustable high-resistance circuit, which, for example, enables us to realize a pole-zero-cancellation in the analog chain. A two-dimensional ASIC with a fast read-out scheme and a one-dimensional ASIC with an improved analog design are developed and verified. With the latter ASIC connected with a CdTe detector, we have obtained a radioactive source spectrum with an energy resolution of 4.6 keV (FWHM) at 59.5 keV.

Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 μm. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance.

A very low-power CMOS mixed-signal IC for implantable pacemaker applications

Low power consumption is crucial for medical implant devices. A single-chip, very-low-power interface IC used in implantable pacemaker systems is presented. It contains amplifiers, filters, ADCs, battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control. A few circuit techniques are proposed to achieve nanopower circuit operations within submicron CMOS process. Subthreshold transistor designs and switched-capacitor circuits are widely used. The 200 k transistor IC occupies 49 mm/sup 2/, is fabricated in a 0.5-/spl mu/m two-poly three-metal multi-V/sub t/ process, and consumes 8 /spl mu/W.

Trends in the design of spectroscopy amplifiers for room temperature solid State detectors

This paper discusses the present trends in the design of low-noise front-end systems for room temperature semiconductor detectors. The technological advancement provided by submicron CMOS and BiCMOS processes is examined from several points of view. The noise performances are a fundamental issue in most detector applications and suitable attention is devoted to them for the purpose of judging whether or not the present processes supersede the solutions featuring a field-effect transistor as a front-end element. However, other considerations are also important in judging how well a monolithic technology suits the front-end design. Among them, the way a technology lends itself to the realization of additional functions, for instance, the charge reset in a charge-sensitive loop or the time-variant filters featuring the special weighting functions that may be requested in some applications of CdTe or CZT detectors.

Impact of metallisation on resistor matching in a 0.35 μm analogue CMOS process

Feature size control in deep sub-micron CMOS processes requires attention to the local and global metal density. This can lead to the placement of metal on top of sensitive analogue components. In this study we report the first results on the impact of metal coverage on the matching of high and low ohmic polysilicon resistors in a 0.35 μm analogue CMOS technology. A significant degradation in matching is observed, especially when matched resistors have unequal metal coverage. In contrast to reported results in one earlier other technology, the mismatch degradation is not strongly influenced by process changes such as modified sinter temperature or the presence of titanium in the metallisation. Limited data show that the effect is also seen in bulk silicon resistors, with a larger magnitude. It is demonstrated that the most likely explanation for the effect is the impact of stress from the metal film on the silicon resistance. A consequence of the effect is that in analogue designs metal must be kept a sufficient distance (10 μm in this process) away from matched resistor pairs.

Reduced Impact of Induced Gate Noise on Inductively Degenerated LNAs in Deep Submicron CMOS Technologies

Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the-art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used.

Simulations for thermal warpage and pressure nonlinearity of monolithic cmos pressure sensors

The operation function of a piezoresistive pressure sensor utilizes a voltage output to detect the magnitude of pressure. The basic design concept for monolithic pressure sensors is to fabricate a standard submicron CMOS process with appropriate modifications to integrate on-chip signal conditioning circuits with anisotropic-etched piezoresistive sensing elements. In this study, thermal stress simulations with applied pressure loadings are used to estimate the electromechanical behavior of a new monolithic sensing element concept design. The major tasks are to predict the ripple deformation of a silicon diaphragm due to the thermal residual stresses from multiple passivation layers and estimate the pressure nonlinearities on the transducer. More detailed approaches with design and performance concerns are also discussed.

A 1.4-v 10-bit 25-ms/s pipelined adc using opamp-reset switching technique

A low-voltage opamp-reset switching technique (ORST) that does not use clock boosting, bootstrapping, switched-opamp (SO), or threshold voltage scaling is presented. This technique greatly reduces device reliability issues. Unlike the SO technique, the opamps stay active for all clock phases and, therefore, the ORST is suitable for high-speed applications. This new switching technique is applied to the design of a 10-bit 25-MS/s pipelined analog-to-digital converter (ADC). The prototype ADC was fabricated in a 0.35-/spl mu/m CMOS process and demonstrates 55-dB signal-to-noise ratio, 55-dB spurious-free dynamic range, and 48-dB signal-to-noise-plus-distortion ratio performance with a 1.4-V power supply. The total power consumption is 21 mW. The ADC's minimum operating power supply is 1.3 V (|V/sub TH,P/| = 0.9 V) and the maximum operating frequency is 32 MS/s. The ORST is fully compatible with future low-voltage submicron CMOS processes.

A high-speed low-noise transimpedance amplifier in a 0.25 μm CMOS technology

We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4 fC, an input capacitance of 4 pF and a transresistance of 135 kΩ, we have measured an output pulse fall time of 3 ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130 K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5 ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the construction of a high-intensity proton beam hodoscope for the NA60 experiment. The chip has been laid out using special techniques to improve its radiation tolerance, and it has been irradiated up to 10 Mrd (SiO 2) without any degradation in the performance.

Obtaining silicide free spacers by optimizing sputter etch for deep submicron CMOS processes

In this paper, we have shown that the sputter etch before cobalt deposition during the silicide processing of a deep submicron CMOS device fabrication needs to be optimized in order to eliminate a detrimental origin of gate (G) to source (S)/drain (D) bridging. It is known that Co cannot reduce even a thin layer of native oxide. Therefore, it is necessary to ensure that Co is deposited on a very clean Si surface. To ensure this, an in-situ sputter etch is commonly conducted before Co deposition. It is observed that this sputter etch process can sputter Si from the S/D area and deposit them on the sidewall spacer (SWS). This sputtered Si in turn will react with deposited Co and form silicide. The worst case leakage currents from poly-Si to composite for long (10 m) and narrow (0.18 micron) poly lines are shown to be on the order of milliampere. Transmission electron microscope (TEM) micrographs included show the existence of cobalt silicide layers (/spl sim/8 nm thick) over sidewall spacer. The silicide thickness on the sidewall spacer is correlated with resistance value calculated from current and voltage (I-V) measurements. The need for optimizing the sputter etch recipe has been validated by TEM and I-V measurements.

Generation of mobile hydrogenous ions in gate oxideand their potential applications

It has been reported that mobile hydrogenous ions can be formed in the oxide after exposure to temperatures of 1100–1300°C for 30 min. It is investigated whether these ions can be created in a standard MOSFET fabricated by a submicron CMOS process, without using such a high thermal budget. The potential use of a MOSFET as a non-volatile memory device is explored and problems are highlighted.

Experimental studies of the noise properties of a deep submicron CMOS process

Deep submicron CMOS technologies are presently very attractive for front-end electronics design, because of their features in terms of low power consumption, high integration density and radiation tolerance. A full understanding of the noise parameters of the devices belonging to these technologies is needed to confirm that they can be used to implement low-noise analog blocks. This paper describes a noise test system, which was purposely developed to measure the noise voltage spectrum of CMOS devices in a frequency range extending up to 100 MHz. As an application example, the results of the experimental characterization of the noise properties of a 0.35 μm CMOS process are presented.

A high speed, precision voltage buffer in a submicron CMOS process

A new buffer architecture was introduced by Comer and Comer (1998, International Journal of Electronics, 84, 345). This buffer uses an active feedback network based on a transconductance amplifier. An implementation of the new buffer was done in a CMOS process. The buffer was intended for the output stage of a 10-bit video digital-to-analogue converter. The circuit was fabricated on the American Microsystems 0.6 μm process. Design specifications called for a gain accuracy of 0.1%, an offset voltage shift of no more than 1mV over a commonmode input range of 50% of supply voltage and a bandwidth of 500MHz. The actual circuit showed a gain error of less than 0.1%, a common-mode offset variation of less than 2mV, and a bandwidth of 450MHz.

Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology

This letter presents a deep submicron CMOS process that takes advantage of phosphorus transient enhanced diffusion (TED) to improve the hot carrier reliability of 3.3 V input/output transistors. Arsenic/phosphorus LDD nMOSFETs with and without TED are fabricated. The TED effects on a LDD junction profile, device substrate current and transconductance degradation are evaluated. Substantial substrate current reduction and hot carrier lifetime improvement for the input/output devices are attained due to a more graded n/sup -/ LDD doping profile by taking advantage of phosphorus TED.