Stuck-open Faults In CMOS Circuits Research Articles

Reliable detection of CMOS stuck-open faults due to variable internal delays

Testable designs for detecting single stuck-open faults in CMOS circuits have been proposed so that the tests remain valid even in the presence of unequal delays in the circuit. Existing approaches require the CMOS gate to be internally modified and are thus suitable for future chip designs. This paper proposes two versatile designs that can be adapted for both existing chips and new chip designs. A 3-sequence test set and a 2-sequence test set are derived for the proposed designs to reliably detect stuck-open faults.

BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count

This paper presents a built-in self-test (BIST) scheme for detecting all robustly testable multiple stuck-open faults confined to any single complex cell of a CMOS circuit. The test pattern generator (TPG) generates all n . 2n single-input-change (SIC) ordered test pairs for an n-input circuit-under-test (CUT) contained in a sequence of length 2n.2n. The proposed design is universal, i.e., independent of the structure and functionality of the CUT. A counter that counts the number of alternate transitions at the output of the CUT, is used as a signature analyzer (SA). The design of TPG and SA is simple and no special design- or synthesis-fortestability techniques and/or additional control lines are needed.

Cellular automata as a BIST structure for testing CMOS circuits

Two-patterns are required to test single stuck-open faults in CMOS circuits, while detection of multiple stuck-open faults requires the application of three-patterns. The regular, modular and cascadable structure of cellular automata (CA) has been proposed as a built-in self-test (BIST) structure for on-chip generation of two-pattern and three-pattern test vectors. An analytical tool has been developed to characterise the properties of CA as a test pattern generator for CMOS circuits. The conditions to generate exhaustive two-patterns and three-patterns of n-bits have been investigated. Based on matrix algebraic analysis, it is shown that a specific class of CA satisfying this condition can be employed as a BIST structure for testing CMOS circuits. A lower bound on CA size has been analytically established. Criteria for the selection of the most desirable CA structure have also been presented along with the experimental results for a set of real-life circuits.

Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits

A sequence of input vectors which detects all transistor stuck-open faults in a CMOS combinational circuit is a complete test sequence. Given a complete set of two-pattern tests for transistor stuck-open faults in a CMOS circuit, it is shown that a complete test sequence of minimum length can be obtained efficiently. A precise description of this problem and examples to illustrate the method are presented. >