Cellular automata as a BIST structure for testing CMOS circuits

Abstract

Two-patterns are required to test single stuck-open faults in CMOS circuits, while detection of multiple stuck-open faults requires the application of three-patterns. The regular, modular and cascadable structure of cellular automata (CA) has been proposed as a built-in self-test (BIST) structure for on-chip generation of two-pattern and three-pattern test vectors. An analytical tool has been developed to characterise the properties of CA as a test pattern generator for CMOS circuits. The conditions to generate exhaustive two-patterns and three-patterns of n-bits have been investigated. Based on matrix algebraic analysis, it is shown that a specific class of CA satisfying this condition can be employed as a BIST structure for testing CMOS circuits. A lower bound on CA size has been analytically established. Criteria for the selection of the most desirable CA structure have also been presented along with the experimental results for a set of real-life circuits.