Reliable detection of CMOS stuck-open faults due to variable internal delays

Abstract

Testable designs for detecting single stuck-open faults in CMOS circuits have been proposed so that the tests remain valid even in the presence of unequal delays in the circuit. Existing approaches require the CMOS gate to be internally modified and are thus suitable for future chip designs. This paper proposes two versatile designs that can be adapted for both existing chips and new chip designs. A 3-sequence test set and a 2-sequence test set are derived for the proposed designs to reliably detect stuck-open faults.