Stuck-on Faults Research Articles

Efficient detection of transistor stuck-on faults in CMOS circuits using low-overhead single-ended ring oscillators

Very large-scale integration technology is accelerating the growth and prevalence of nanoscale devices worldwide, but at the same time facing technical challenges in terms of fault detection due to the compact size of chips. Thus, the detection of faults in chips caused by limitations of the manufacturing process or operational aspects of the architecture is obligatory to assess the effective performance of devices. In this paper, two single-ended ring oscillator (SERO)-based transistor stuck-on (TSON) fault detection methods are proposed for complementary metal–oxide–semiconductor (CMOS) circuits. The SERO is used as a current-controlled and voltage-controlled oscillator in method 1 and 2, respectively, reducing the circuit overhead of the detection block. Simulations are carried out using Cadence Virtuoso in 90-nm technology. The results show that both methods can successfully detect TSON faults in CMOS circuits based on the oscillatory behavior of the SERO. Moreover, these methods avoid the need to sense the output voltage level or quiescent current, which increases the possibility of successful fault detection, especially for submicron-level structures by avoiding improper logic and unreliable current values. Test vectors and fault locations can also be easily identified using the proposed methods, reducing the implementation complexity of CMOS fault detection techniques.

Handling Stuck-at-Fault Defects Using Matrix Transformation for Robust Inference of DNNs

Matrix-vector multiplication is the dominating computational workload in the inference phase of deep neural networks (DNNs). Memristor crossbar arrays (MCAs) can efficiently perform matrix-vector multiplication in the analog domain. A key challenge is that memristor devices may suffer stuck-at-fault defects, which can severely degrade the classification accuracy. Earlier studies have shown that the accuracy loss can be recovered by utilizing additional hardware or hardware aware training. In this article, we propose a framework that handles stuck-at-faults using matrix transformations, which is called the MT framework. The framework is based on introducing a cost metric that captures the negative impact of the stuck-at-fault defects. Next, the cost metric is minimized by applying matrix transformations $T$ . A transformation $T$ changes a weight matrix $W$ into a new weight matrix $\widetilde {W}= T(W)$ . In particular, a row flipping transformation, a permutation transformation, and a value range transformation are proposed. The row flipping transformation results in that stuck-off (stuck-on) faults are translated into stuck-on (stuck-off) faults. The permutation transformation maps small (large) weights to memristors stuck-off (stuck-on). The value range transformation is based on reducing the magnitude of the smallest and largest elements in the weight matrices, which results in that the stuck-at-faults introduce smaller errors. The experimental results demonstrate that the MT framework is capable of recovering 99% of the accuracy loss on both the MNIST and CIFAR-10 datasets without utilizing hardware aware training. The accuracy improvements come at the expense of an $8.19\times $ and $9.23\times $ overhead in power and area, respectively. Nevertheless, the overhead can be reduced with up to 50% by leveraging hardware aware training.

Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs

Manufacturing defects that do not affect the functional operation of low power integrated circuits (ICs) can nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive bridges between the power networks can impair the power saving capability of power-gating designs. For quantifying the impact of such faults on the power savings of power-gating designs, we propose a diagnosis technique that targets bridges between the power networks. The proposed technique is based on the static power analysis of a power-gating design in stand-by mode and it utilizes a novel on-chip signature generation unit, which is sensitive to the voltage level between power rails, the measurements of which are processed off-line for the diagnosis of bridges that can adversely affect power savings. We explore, through SPICE simulation of the largest IWLS’05 benchmarks synthesized using a 32 nm CMOS technology, the tradeoffs achieved by the proposed technique between diagnosis accuracy and area cost and we evaluate its robustness against process variation. The proposed technique achieves a diagnosis resolution that is higher than 98.6% and 97.9% for bridges of ${R}~{\gtrsim }~{10~{ M}\Omega }$ (weak bridges) and bridges of ${R~\lesssim~10~{ M}\Omega }$ (strong bridges), respectively, and a diagnosis accuracy higher than 94.5% for all the examined defects. The area overhead is small and scalable: it is found to be 1.8% and 0.3% for designs with 27 K and 157 K gate equivalents, respectively.

Determination of maximum solar power under shading and converter faults—A prerequisite for failure-tolerant power management systems

According to the fact that the performance of power management systems depends on generation forecasts, a scheme is proposed to detect the shading fault and the converter failure in a PV system and determine the maximum available solar power in the presence of these faults. Since the MPP of a PV array under uniform and partial shading faults is smaller than that of non-shading condition, for MPP tracking operations, difference between acquired and estimated power is an indicator for the shading fault. However, when the load power is small enough to be satisfied by the shaded PV array, the defined voltage ratio is used to detect the shading fault. In the case of shading fault, maximum available solar power is determined based on the output power of the PV system. Converter failure, which is modeled as the switch stuck-open fault or the switch stuck-on fault, is also considered in this paper. It is shown that under the switch stuck-open fault, the output power of the PV system will be zero; while, under the switch stuck-on fault, the output power shows a sinusoidal behavior. Based on the PV system power analysis, a procedure is also proposed to detect the converter failure and determine the maximum available solar power under this fault.

OR-Bridging Fault Identification and Diagnosis for Exclusive-OR Sum of Products Reed-Muller Canonical Circuits

Problem statement: The faults in digital circuit can be classified broadly as single stuck-atfaults, multiple stuck-ay-faults, stuck-open faults, stuck-on faults, path delay faults, transient faults. Extensive research had been carried out in the field of testing of digital circuits to limit the number of input vectors. The cardinality of the test vectors proposed by many authors was quite high for large number of input variables. In this study a testable circuit with a small test set for detection and diagnosis of OR-bridging type fault in Reed-Muller canonical Exclusive-OR Sum of Products logic circuits, independent of the function for a given number of inputs had been proposed. Approach: A network structure comprising a set of Exclusive-OR gates and gates and a couple of auxiliary outputs were considered. The circuit as well as the test vectors were simulated by MATLAB coding. The faultfree and OR-bridging faults involving any two lines of control and data lines were then simulated. The outputs were represented in a compact decimal form for ease of tabulation. Two quantitative indices for comparison of results had also been discussed. Simulation and analysis for various random functions had been presented. Results: From the test results it was found that the identifiability for the set of random functions tested was more than 90% with just n + 5 test vectors compared to 2n test vectors required for conventional testing. It was also observed that even though the overall distinguishabililty factor was in the range of 45-80%, the individual set distinguishability was more than 90%. Conclusion: The proposed scheme had reduced the possibility of unidentifiable faults for the specified type of function. The location was also diagnosed through the output set. The analysis and diagnosis had been done through compact tabulation and two quantification indices.

Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests

Ternary content addressable memory (TCAM) plays an important role in various applications for its fast lookup operation. This paper proposes several comparison fault models (i.e., the faults cause Compare operation fail) of TCAMs based on electrical defects, such as shorts between two circuit nodes and transistor stuck-open and stuck-on faults. Two March-like tests for detecting comparison faults are also proposed. The first March-like test requires 4N Write operations, 3N Erase operations, and 4N+2B Compare operations to cover 100% of targeted comparison faults for an NtimesB-bit TCAM with Hit output only. The second March-like test requires 2N Write operations, 2N Erase operations, and 4N+2B Compare operations to cover 100% of targeted comparison faults for an NtimesB-bit TCAM with Hit and Priority Address Encoder outputs. Compared with the previous work, the proposed tests have lower time complexity for typical TCAMs; they can be used to test TCAMs with different comparator structures; and their time complexities are independent of the number of stuck-on faults. Also, they can cover delay faults in comparison circuits

Testable Designs of Multiple Precharged Domino Circuits

Domino CMOS circuits are an option for speeding up critical units. An inherent problem of Domino logic is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of a circuit can violate the noise margins and cause erroneous responses at the output. The dominant solution to this problem is the multiple precharging of the gate's internal nodes. However, the added precharge transistors are not testable for stuck-open faults. Undetectable stuck-open faults at these transistors may cause noise margins reduction and consequently may affect the reliability of the circuit since its operation in the field will be sensitive to environmental factors such as noise. In this paper, we propose new multiple precharging design schemes that enhance Domino circuits' testability with respect to transistor stuck-open and stuck-on faults

Fault characterisation and testability issues of complementary pass transistor logic circuits

Testability of basic and complex logic gates employing complementary pass transistor logic (CPL) circuits under various single stuck faults has been investigated. Results show that all stuck-on faults, bridging faults and more than 90% of stuck-at faults in basic CPL gates are detectable only by current monitoring, generally known as IDDQ testing. It is also shown that all stuck-open faults in the basic CPL gates are detectable only by logic monitoring using an appropriate two-pattern test. Testability analysis of a CPL full-adder under a single stuck-on fault condition shows that stuck-on faults on all MOS transistors of the SUM logic and the CARRY logic circuit can be detected by signal source current monitoring with appropriate test vectors. Similarly, stuck-at faults on all MOS transistors of the full-adder can be detected by current monitoring only, and stuck-open faults on all MOS transistors of the full-adder can be detected by an appropriate two-pattern test. It is concluded that signal source current monitoring (IDDQ testing) is the best method for fault detection in CPL circuits, and gives more than 94% fault coverage of stuck-at, stuck-on and bridging faults; and logic monitoring gives 100% fault coverage of stuck-open faults.

Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 code checkers

In this paper we present new strongly code-disjoint (SCD) and strongly fault-secure (SFS) checkers for the 2-out-of-3 and1-out-of-3 codes. They are implementedin Domino CMOS logic andtake into account a comprehensive fault model consisting of stuck-at, transistor stuck-open andtransistor stuck-on faults. The proposedcheckers are the first known SCD/SFS 2-out-of-3 and 1-out-of-3 code checkers in the open literature that consider the above fault model without suffering from static power consumption.

On the properties of the input pattern fault model

A review of traditional IC failure analysis techniques strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard single stuck-line- (SSL-) based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting nontargeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

Testing Configurable LUT-Based FPGAs

A novel approach to testing lookup table (LUT) based field programmable gate arrays (FPGAs) is proposed in this paper. A general structure for the basic configurable logic array blocks (CLBs) is assumed. We group k CLBs in the column into a cell, where k denotes the number of inputs of an LUT. The whole chip is configured as a group of one-dimensional iterative logic arrays of cells. We assume that in each linear cell array, there is at most one faulty cell, and that multiple faulty CLBs in the same cell can be detected. For the LUT, a fault may occur at the memory matrix, decoder, input or output lines. The switch stuck-on and stuck-off fault models are adopted for multiplexers. New conditions for C-testability of programmable reconfigurable arrays are also derived. Our idea is to configure the cells so as to make each cell function bijective. This property is helpful for applying pseudoexhaustive test patterns to each cell and propagating errors to the observable outputs. In order to detect all the faults defined, k+2 configurations are required, and the resulting number of test patterns is 2(superscript k). A novel built-in self-test structure is also proposed in this paper. The input patterns can be easily generated with a k-bit counter. The number of configurations for our BIST structures is 2k+4. Our BIST approaches also have the advantage of requiring fewer hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, three test sessions are required. However, the maximum number of configurations for diagnosing a faulty CLB is k+4.

Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits

Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits

Testable designs of one-count generators

Testable realizations of One-Count Generators (OCGs) with respect to an extended fault model, including the stuck-at, transistor stuck-open, and transistor stuck-on faults using current monitoring, are presented. These implementations are made up of testable components which are commonly found in current CMOS libraries. A new design method for OCGs is given which offers the ability to apply a desired robust pair of vectors at the inputs of every element of the OCG (and hence any desired single vector to them), as well as the ability to propagate the effect of any single fault to a primary output of the OCG.

ＣＭＯＳスタティックメモリ回路の電流テスト手法

In this paper, we discuss a current testing method, which aims to reduce testing costs on CMOS Static RAMs (SRAMs). As the fault models on a memory cell, we assume a hard short between two signal lines, a hard open on signal line, a transistor stuck-on fault, and a transistor stuck-open fault. Proposed test method is based on the simulation results of electrical behavior on the faulty memory cell. In this test method, decoder circuits and bit lines are modified to drive all the memory cells of SRAMs simultaneously. Since the faults are detected by only observing the power supply current, the test sequence becomes simple, and it does not dependent on the size of the memory cell array.

Detection of multiple faults using SSFTS in CMOS logic circuits

With the increasing density of CMOS VLSI circuits, it is necessary to test for the combinations of different multiple faults. This paper studies the possibility of using single stuck-at fault test set (SSFTS) to detect multiple faults and their combinations. The paper shows that a single stuck-at-fault test set can detect single and multiple self-feedback bridging faults, combinations of feedback bridging, input bridging and stuck-on faults when current monitoring is done. We also prove that a single stuck-at fault test set can detect the combination of single stuck-open fault and some other faults like bridging and stuck-on faults when both logic and current monitoring are done.

Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults

This work presents a design technique for CMOS static and dynamic checkers (to be used in self-checking circuits), that allows the detection of all internal single transistor stuck-on and bridging faults causing unacceptable degradations of the circuit dynamic performance (but not logical errors). Such a technique exploits simple voltage detector circuits to make sure that the intermediate faulty voltages inevitably produced by the faults of interest are always propagated at the checker output as logic errors. With the use of our technique, the main disadvantages of static checkers, so far preventing their use in practical applications, are overcome. The method has been applied to the particular case of two-rail (static as well as dynamic) checkers and its validity has been verified by means of electrical level simulations.

Manifestations of faults in single- and double-BJT BiCMOS logic gates

Combining the inherent advantages of bipolar and CMOS, BiCMOS is emerging as a major technology for high-speed, high-performance, digital and mixed-signal applications. Logic behaviour of single- and double-BJT BiCMOS devices under transistor-level shorts and opens is examined. In addition to sequential behaviour, some stuck-open faults exhibit increased delay. While most stuck-on faults can be detected by logic level testing, some of them can only be detected by monitoring the power supply current (I DDQ monitoring). A stuck-open fault in double-BJT BiCMOS device manifesting as enhanced dynamic I DD current is shown. The faulty behaviour of bipolar (TTL) and CMOS logic families is compared with BiCMOS. Testability of both single- and double-BJT BiCMOS devices are discussed along with a design for a testability approach for detecting stuck-open faults in S-BJT BiCMOS devices

A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations

We present a strongly code disjoint (SCD) built-in current sensor (BICS) based on self-exercising concept. The integration of this SCD BICS with a self-checking circuit achieves the totally self-checking goal in static CMOS realizations, even in the presence of stuck-on and bridging faults, and results in a strongly fault-secure realization. Low-cost and high fault coverage is attractive for many high reliability and critical applications. >

A concurrent error detection IC in 2-μm static CMOS logic

When a comprehensive fault model is considered, static CMOS VLSI has long been prohibited from realizing concurrent error detecting (CED) circuits due to the unique analog faults (bridging and stuck-on faults). In this paper, we present the design, fabrication and testing of an experimental chip containing the integration of a totally self-checking (TSC) Berger code checker and a strongly code disjoint (SCD) built-in current sensor (BICS). This chip was fabricated by MOSIS using 2 /spl mu/m p-well CMOS technology. In chip tests, all implanted faults, including analog faults, were detected as expected. We also show that the self-exercising mechanism of the SCD BICS is indeed functioning properly. This is the first demonstration of a working static CMOS CED chip. >

SWiTEST: a switch level test generation system for CMOS combinational circuits

Switch level test generation (SLTG) is potentially more powerful than conventional gate level test generation (GLTG) or CMOS circuits. Over the last decade much research has been carried out on SLTG. However to date no widely accepted SLTG system exists. The objectives of this work are to analyze the various problems associated with SLTG, to identify a feasible way to deal with these problems, and to develop an efficient and useful SLTG system for combinational circuits. The basic idea is to make use of as many GLTG concepts as possible without modeling a CMOS circuit at the gate level. Based on the analysis of CMOS circuits and faults, a SLTG system called SWiTEST has been developed. This system can deal with bridging, transistor stuck-open, transistor stuck-on and stuck-at faults. It employs both logic and current (IDDQ testing) monitoring and takes into account the invalidation problem associated with stuck-open tests. The framework of this system is PODEM-based. To be applicable to switch level circuits, the basic PODEM algorithm has been enhanced to deal with concepts such as multiple objective selection, search-based backtracing and incremental event-driven logic implication. Experimental results indicate that SWiTEST is quite efficient in both CPU time and memory usage. >