Stuck-at Faults Research Articles

Efficient and Optimized Methods for Alleviating the Impacts of IR-Drop and Fault in RRAM Based Neural Computing Systems

Resistive switching random access memory (RRAM) shows its potential to be a promising candidate as the basic in-memory computing unit for deep neural networks (DNN) accelerator design due to its non-volatile, low power, and small footprint properties. The RRAM based crossbar array (RRAM CBA) is usually employed to accelerate DNN because of its intrinsic characteristic of executing multiplication-and-accumulation (MAC) operation according to Kirchhoffs' law. However, some major non-ideal effects including IR-drop and Stuck-at-Faults (SAF) in real RRAM CBA are typically ignored in the DNN accelerator design because of the considerations of training speed and design closure. Such non-ideal effects will conduct the variations of output column current and voltage and further cause serious degradation in computing accuracy. Thus, direct mapping from the weights of DNN model without considering the IR-drop and SAF to RRAM CBA is unrealistic. In this work, two efficient and optimized methods including adding additional tunable RRAM row and Trans-impedance amplifier (TIA) based RRAM are proposed to recover the computation accuracy with a view to reducing variation of the output column current of the RRAM CBA and output voltage of the TIA in each column respectively. The two optimized methods are evaluated in different sizes of RRAM CBA and different resistance levels of RRAM cell. The simulation results show that the two optimized methods can further suppress the degradation of computing accuracy induced by IR-drop and SAF for LeNet-5 with the MNIST dataset and VGG16 with the CIFAR-10 dataset.

Construction of complete minimal test set for single intra-level bridging and stuck-at faults in reversible circuits

Reversible logic computing is gaining enough interest in the field of low-power circuit design technology. Moreover, the concept of reversible computing is widely used in quantum circuit computation. Therefore, it has motivated researchers to explore reversible logic as a circuit design alternative. Several problems of synthesis and optimisation of the reversible circuits have been reported in the present literature. In this context, the testing plays an important role in the effective performance of these circuits. For detecting all possible faults in the reversible circuits, numerous fault models have been proposed, where many of the proposed fault models common to conventional logic circuits. In this paper, we consider the problem of testing in the NCT or GT library-based reversible circuits with respect to an efficient test set generation for single intra-level bridging faults and single stuck-at faults. The proposed test generation method has been developed based on the concept of one-to-one mapping mechanism (reversible circuit property). Finally, experimental results show that the generated test is capable of 100% fault coverage for both the fault models and also the results are compared with the existing methods for analysing the test set size.

A hypergrid based adaptive learning method for detecting data faults in wireless sensor networks

In wireless sensor networks (WSNs), data anomalies/faults often occur due to the limited resources and unreliability of sensor nodes. Many traditional anomaly detection methods are designed in a batch manner, but for the nature of streaming data in WSNs, continuous anomaly detection method is preferred. Existing methods often detect only a single type of faults but cannot detect multiple types of faults that actually are more common in the sensor data. Therefore, this paper provides a Hypergrid based Adaptive Detection of Faults (HADF) method, which adopts hypergrid and statistical analysis to recognize three types of faults in the sensor data, including outliers, stuck-at faults, and noisy faults. HADF is a distributed method running on sensor nodes, which can reduce the influence of concept drift in unstable streaming data through combining both lazy leaning and continuous learning to adaptively update its normal profile. In the experimental study, we have manually inserted different types of faults into two real-world datasets, and the results demonstrate that HADF achieves higher accuracy with reasonable efficiency for detecting the data faults than four counterpart methods.

Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

The features of the concurrent error-detection systems of combinational logic circuits based on the search for groups of symmetrically-independent outputs construction

The authors of the article found that in the use of classical sum codes (Berger codes) and a some of their modifications in the combinational circuits testing organization it is possible to detect both unidirectional and part of non-unidirectional errors in the data vectors. It is shown that it is possible to search for such groups of outputs of combinational circuits where only symmetrical errors occur due to stuck at-faults of elements of the internal structure of the circuits. Such groups of outputs are designated as symmetrically-independent outputs (SI-groups of outputs). The conditions of belonging of the group of outputs of the combinational circuits to the SI-groups of outputs are determined. It is shown that each SI-group of outputs can be controlled using a separate testing subsystem based on the code with the detection of any non-symmetrical errors (in particular, and any non-symmetrical errors up to certain multiplicities). The ways of searching for SI-groups of outputs in the combinational circuits testing organization are presented

Tests with Stuck-At and Shift Faults on Circuit Inputs

We investigate left-shifts of variables in Boolean functions and stuck-at faults. Some bounds of Shannon functions are established, producing the minimum test lengths for detection and diagnosis of any n-variable Boolean function with respect to a given fault source. (The Shannon function of the test length is the maximum of the minimum test lengths over all n-variable Boolean functions.) A left-shift in an n-variable Boolean function simultaneously increments the indexes of all the variables by a natural number and substitutes some constants for variables with indexes greater than n. The Shannon function of the relevant test is shown to be exactly of length 2; the order of growth of the Shannon function of the length of the diagnosis test is $$ \Theta \left(\sqrt{2^n}\right). $$ With the variables left-shifted by k places, 1 ≤ k ≤ n, the Shannon function $$ {L}^{diagn}\left({U}_{n,k}^{shifts},n\right) $$ of the length of the complete diagnosis test has the following bounds: $$ \min \left({2}^k-1,{2}^{n-k}\right)\le {L}^{diagn}\left({U}_{n,k}^{shifts},n\right)\le \min \left({2}^k,{2}^{n-k}+1\right). $$ The article also considers local stuck-at faults of multiplicity k on the inputs of k-input, one-output circuits realizing a Boolean function. An asymptotic expression is derived for the log Shannon function of the diagnosis test length $$ {\log}_2{L}^{diagn}\left({U}_k^{lc},n\right)\sim k\ \mathrm{as}\ n\to \infty, k=k(n)\to \infty, \kern1em 1\le k\le n/2,{\log}_2n=o(k). $$ An asymptotic lower bound of the Shannon function of the diagnosis test length with stuck-at faults on circuit inputs is shown to be Ldiagn(Uc, n) ≥ 2 ⋅ 2[n/2] ⋅ (1 + o(1)) as n → ∞ .

Fault Detection Architectures for Inverted Binary Ring-LWE Construction Benchmarked on FPGA

Ring learning with errors (RLWE) is an efficient lattice-based cryptographic scheme that has worst-case reduction to lattice problem, conjectured to be quantum-hard. Ring-BinLWE is an optimized variant of RLWE problem using binary error distribution, resulting in highly-efficient hardware implementation. Efficient and low-complexity architectures in hardware, thwarting natural and malicious faults, are essential for lattice-based post-quantum cryptography (PQC) algorithms. In this brief, we explore efficient fault detection approaches for implementing the Ring-BinLWE problem. This brief, for the first time, investigates fault detection schemes for all three stages of RLWE encryption. Utilizing the stuck-at fault model, we employ recomputing with encoded operands schemes to achieve high error coverage. We simulate and implement our schemes on a field-programmable gate array (FPGA) platform. Our schemes provide low hardware overhead (area overhead of 15.74%, delay overhead of 7.74%, and power consumption overhead of 4.06%), with high error coverage, which can be suitable for resource-constrained as well as high-performance usage models.

Single stuck-at-faults detection using test generation vector and deep stacked-sparse-autoencoder

This paper proposed a new method for testing digital circuits without hardware implementation. This data-based method detects hundreds of single stuck-at faults in the ALU circuits, utilizing deep stacked-sparse-autoencoder (SSAE). ATALANTA software is one of the free automatic test pattern generation tools which cover faults in high accuracy. Test vectors which are extracted from bench circuits via ATALANTA software are the key point of the paper. Fault detection is introduced as a two-class problem. SSAE network is trained using the test vectors. Dimension reduction is done automatically in SSAE. Network performance is tested by changing sparse coefficients, number of stacked autoencoder and data augmentation. The results of this step are compared with the traditional multilayer perceptron classification. In this method, unlike SSAE, a manual method of reducing the dimension and extracting the feature is used. Fault coverage of ATALANTA software is over than 94%. Finally, the results obtained from the deep neural network show its significant performance in the circuit faults detection automatically.

A distributed sensor-fault detection and diagnosis framework using machine learning

The objective of this work is to design a sensor-fault detection and diagnosis system for the Internet of Things and Cyber-Physical Systems. The challenge is, however, achieving this objective within the limited computation, memory, and energy resources of the sensors. More importantly, the detection of faults is time-sensitive, whereas the diagnosis does not necessarily need to be fast. We propose a distributed sensor-fault detection and diagnosis system based on machine learning algorithms where the fault detection block is implemented in the sensor in order to achieve output immediately after data collection. This block consists of an auto-encoder to transform the input signal into a lower-dimensional feature vector, which is then provided to a Support Vector Machine (SVM) for classification as normal or faulty. Once detected, fault diagnosis is performed at a central node, such as a network server, to reduce the computational load on the sensor. In this work, a Fuzzy Deep Neural Network (FDNN) is used for diagnosis to provide further information, such as the type of fault. Here, the input propagates through a deep neural network and a fuzzy representation process. The output of these two components is then fused through densely connected layers. This multi-modal technique learns high-level representations in the data that are missed by conventional methods. To assess the performance of the proposed model, we utilize data obtained from a healthy temperature-to-voltage converter that are then injected with five types of fault: drift, bias, precision degradation, spike, and stuck faults. The performance from fault detection is analyzed in terms of detection accuracy, area under the ROC curve (AUC-ROC), false positive rate, and F1 score. Furthermore, the efficiency of fault diagnosis is shown by the classification accuracy parameter. The experimental results show the efficiency of the proposed fuzzy learning-based model over classic neuro-fuzzy and non-fuzzy learning approaches.

On-line self-test mechanism for Dual-Core Lockstep System-on-Chips

The Dual-Core Lockstep configuration is largely employed in safety-critical System-on-Chips for the sake of compliance with functional safety standards. Such configuration includes two processor cores paired together, always fed with the same identical inputs and their outputs are continuously compared by a set of comparators. However, permanent faults affecting the comparators may invalidate the system functionalities, thus in-field self-test mechanisms are mandatory. In this paper, different in-field self-test solutions are first discussed. Then, a hybrid hardware-software scheme for the on-line testing of the lockstep logic is proposed. Such a solution leverages test programs developed according to the Software-Based Self-Test (SBST) approach, used in conjunction with a specialized hardware module. The effectiveness of this approach was assessed on a modified version of the OpenRISC 1200 processor. Exhaustive experiments demonstrated that it is possible to achieve a fault coverage of stuck-at faults greater than 99%, while at the same time significantly reduce the area overhead of classical approaches.

Test Chips With Scan-Based Logic Arrays

This article proposes a scan-based test chip architecture targeting the diagnosis of multiple faults consisting of input pattern faults, stuck-at faults, and bridging faults (BFs). The architecture consists of a 2-D array of logic blocks and two sets of scan chains isolating the logic blocks. The scan chains are used to fully control and observe the logic blocks so as to enhance the testability and diagnosability of test chips. An efficient diagnostic procedure composed of two tests is developed to carry out the defect diagnosis process. Evaluation results show that the proposed procedure can always achieve 100% accuracy for single faults. When double faults containing 0, 1, and 2 BFs are considered, the proposed procedure can achieve 100% accuracy for 99.38%, 98.398%, and 97.416% of the faults and achieve perfect resolution for 98.81%, 98.006%, and 97.202% of the faults, respectively. Moreover, no matter how many faults exist, as long as no fault affects the scan registers, the proposed procedure can report all faulty logic blocks.

Construction of Complete Minimal Test Set for Single intra-level Bridging and Stuck-at Faults in Reversible Circuits

Reversible logic computing is gaining enough interest in the field of low-power circuit design technology. Moreover, the concept of reversible computing is widely used in quantum circuit computation. Therefore, it has motivated researchers to explore reversible logic as a circuit design alternative. Several problems of synthesis and optimisation of the reversible circuits have been reported in the present literature. In this context, the testing plays an important role in the effective performance of these circuits. For detecting all possible faults in the reversible circuits, numerous fault models have been proposed, where many of the proposed fault models common to conventional logic circuits. In this paper, we consider the problem of testing in the NCT or GT library-based reversible circuits with respect to an efficient test set generation for single intra-level bridging faults and single stuck-at faults. The proposed test generation method has been developed based on the concept of one-to-one mapping mechanism (reversible circuit property). Finally, experimental results show that the generated test is capable of 100% fault coverage for both the fault models and also the results are compared with the existing methods for analysing the test set size.

Organization of a Fully Self-Checking Structure of a Combinational Device Based on Searching for Groups of Symmetrically Independent Outputs

A new technique is elaborated for building combinational devices with fully self-checking structures, where any kind of single stuck-at faults in internal logical elements is detected. The suggested technique is based on searching for groups of combinational device outputs in which symmetrical errors are impossible (SI groups). When establishing such groups, the developer can choose the implementation options for a self-checking device, each of which assumes the use of a code for failure control with the detection of any unidirectional and asymmetrical errors (identified multiplicities included).

PRESERVE: Static Test Compaction that Preserves Individual Numbers of Tests

A comprehensive test set targets faults of different types to ensure that defects of different types are detected. When test compaction is carried out for such a test set, it is advantageous if the compacted test set contains a compact test set for each fault type separately. In this case, if one (or more) of the fault types is found to be more important to detect, a compact test set for it can be extracted without further processing. This article describes the first test compaction procedure for transition and stuck-at faults, where by construction, the compact test set contains compact test sets for each fault type separately. The experimental results for benchmark circuits demonstrate the ability to compact a comprehensive test set under this condition.

Actuator Faults Estimation for a Helicopter UAV in the Presence of Disturbances

The aim of this paper is to develop robust three-stage extended Kalman filter for a model based on a fault detection and identification for nonlinear hover mode system of helicopter unmanned aerial vehicle. In addition, we show that, in considered systems, the actuator faults are affected by each other motivated in five scenarios simulation results. More precisely, the proposed approach estimates and decouples actuator faults in the presence of external disturbances in nonlinear mathematical model. Moreover, we analyze and identify various faults such as bias fault and also catastrophic faults such as stuck and floating faults. Finally, the simulation results show effectiveness of the proposed robust method for detection and isolation of various actuator faults and differentiating bias and stuck faults.

Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices

Switching lattices are two-dimensional arrays composed of two or four-terminals switches organized as a crossbar array. The idea of using regular two-dimensional arrays of switches for Boolean function implementation was proposed by Akers in 1972. Recently, with the advent of a variety of emerging nanoscale technologies, lattices have found a renewed interest. Emerging technologies allow more complex function integration, thanks to their smaller sizes and advanta geous properties such as zero leakage current, capability to retain data when in power-off state, and almost unlimit edendurance, to name just a few appealing features. Also, implementation of new computing paradigms combining memory and logic becomes possible. However, emerging technologies show a non-negligible defect ratio and higher sensitivity to process and environment variations. The reliability challenges in adopting these technologies need to be investigated. In this paper, we analyze the resilience of switching lattices to stuck-at-fault model (SAF). We first identify the critical switches through an elaborated sensitivity methodology and extensive analysis of the lattice. Next, we propose several techniques to improve lattice resilience in the face of these types of faults, that can be implemented after lattice logic optimization steps.

Cell-Aware Defect Diagnosis of Customer Returns Based on Supervised Learning

In this paper, we propose a new learning-guided approach for diagnosis of intra-cell defects that may occur in customer returns. In the first part of the paper, only static defects modeled by stuck-at faults have been assumed. Several supervised learning algorithms were considered, with various levels of efficiency. In the second part of the paper, we have extended the previous work by dealing with more sophisticated (i.e., dynamic) defects. This time, we concentrated on a Bayesian classification method used for predicting the nature (likelihood to be a good candidate) of each new data instance (defect) that has to be evaluated during the diagnosis process. Results obtained on benchmark circuits, and comparison with a commercial cell-aware diagnosis tool, demonstrate the efficiency of the proposed approach in terms of accuracy and resolution.

ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator

Deep neural networks (DNNs) have gained a strong momentum among various applications. The enormous matrix-multiplication exhibited in the above DNNs is computation and memory intensive. Resistive random-access memory crossbar (RRAM-crossbar) consisting of memristor cells can naturally carry out the matrix-vector multiplication. RRAM-crossbar-based accelerator, therefore, has two orders of magnitude of higher energy-efficiency than conventional accelerators. The imperfect fabrication process of RRAM-crossbars, however, causes various defects and process variations. These fabrication imperfections not only result in significant yield loss but also degrade the accuracy of DNNs executed on the RRAM-crossbars. In this article, we first propose an accelerator-friendly neural-network training method, by leveraging the inherent self-healing capability of the neural network, to prevent the large-weight synapses from being mapped to the imperfect memristors. Next, we propose a dynamic adjustment mechanism to extend the above method for DNNs, such as multilayer perceptrons (MLPs), wherein the imperfect-memristor induced errors can accumulate and magnify through multiple layers. Such off-device training method is a pure software solution, and it is unable to provide enough accuracy for convolutional neural networks (CNNs). Several works propose error-tolerable hardware design by allowing the retraining of CNNs on the RRAM-crossbar. Although this hardware-based on-device training method is effective, the frequent write operation on RRAM-crossbar hurt the endurance of RRAM-crossbars. Consequently, we propose a software and hardware co-design methodology to effectively preserve the classification accuracy of CNN with few on-device training iterations. The experimental results show that the proposed method can guarantee ≤1.1% loss of accuracy for resistance variations in MLP and CNN. Moreover, the proposed method can guarantee ≤1% loss of accuracy even when stuck-at-faults (SAFs) rate = 20%.

Modern design approach of faults (toggling faults, bridge faults and SAT) of reduced ordered binary decision diagram based on combo & sequential blocks

In this Research we are going to develop ROBDD (Reduced Ordered Binary Decision Diagram) designs to detect toggling faults, bridge faults and SAT (Stuck at Fault), Here we are going to develop sequential blocks using ROBDD and applying to the mux to detect stuck at faults and also connecting the combo & Sequential blocks to find the toggling faults by connecting or using automatic test pattern generator. In this research we are going to develop the bridges between the blocks of ROBDD designs and converting them to and or logic to find the bridge faults of the design. Finding bridge and toggle faults are more difficult in logic designs, here we use an advance technique to find the faults of the design by calculating the path delays of the individual blocks of the design. More concentrating on the path delays by using basic stuck at faults methods to refer the faults (toggling and bridge faults) at mux output. In our research the basic design modules are ROBDD circuit of both combinational and sequential blocks are designed and tested using Multiplexer and K-map Simplification Methods. The main purpose of the research to find the faults at all levels of all logic designs which involves in both combinational and sequential blocks of the design.

Design for Stuck-at Fault Testability in Toffoli–Fredkin Reversible Circuits

An intense trade-off arises between testing, hardware and speed of electronic circuits. An efficient design for testability methodology for the detection of stuck-at faults in reversible circuits is presented in this paper by exploiting the properties of Toffoli and Fredkin gates. An ( $$n+1$$ ) dimensional general test set depicted in the paper is found complete for the detection of single and multiple stuck-at faults in the modified circuit. A set of benchmark circuits are taken for experimentation where the proposed work achieved a reduction up to $$25.0\%$$ in gate cost and $$35.8\%$$ in quantum cost when compared to the existing work of the area that proves its efficacy towards the reduction in hardware cost with limited degradation in speed.