Memory Cell Structure Research Articles

The structure and formation of non-volatile memory cells of Superflash

Split-gate embedded Flash memory technology has been around for decades and has become the standard for a wide range of devices, such as microcontrollers and smart cards. Among the, due to a number of advantages, Silicon Storage Technology Super Flash non-volatile memory technology has become the most widespread. This article presents the results of a study of the memory cells structure, examines in detail the principle of their operation and the main technological stages of the production process of forming transistor structures.

Development of a neural network model of an intelligent monitoring agent based on a recurrent neural network with a long chain of short-term memory elements

The article continues to review the approach to designing the architecture of a distributed information monitoring system and quality management of communication services provided by the infrastructures of the Internet of Things and the industrial Internet of Things, based on solutions that support machine-to-machine and human-machine interaction. The development of a neural network model of an intelligent monitoring agent based on a recurrent neural network with a long chain of short-term memory elements is proposed. The matrix structure of the LSTM network memory cell is proposed, which takes into account the spatio-temporal correlation of load parameters associated with the time lag of its propagation and is a matrix of connectivity of LSTM network hyperparameters and accumulated values of load parameters of monitoring nodes in the vicinity of a controlled monitoring node, taking into account the characteristics of the time series of propagation of load in stationarity moments.

Optical readout of charge carriers stored in a 2D memory cell of monolayer WSe2.

Owing to their superior charge retaining and transport characteristics, 2D transition metal dichalcogenides are investigated for practical applications in various memory-cell structures. Herein, we fabricated a quasi-one-terminal 2D memory cell by partially depositing a WSe2 monolayer on an Au electrode, which can be manipulated to achieve efficient charge injection upon the application or removal of external bias. Furthermore, the amount of charge carriers stored in the memory cell could be optically probed because of its close correlation with the fluorescence efficiency of WSe2, allowing us to achieve an electron retention time of ∼300 s at the cryogenic temperature of 4 K. Accordingly, the simplified device structure and the non-contact optical readout of the stored charge carriers present new research opportunities for 2D memory cells in terms of both fundamental mechanism studies and practical development for integrated nanophotonic devices.

Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance

This brief proposes a compact spin-orbit torque magnetic random-access memory (SOT-MRAM) cell structure with high read performance for embedded nonvolatile memory (eNVM) applications. The memory cell is composed of one transistor, two Schottky diodes, two magnetic tunnel junctions (MTJs) and one shared heavy metal (HM) layer, which can be abbreviated as 1T-2D-2MTJ cell. The two MTJs are stacked on the same HM layer for smaller area overhead and configured to be complementary with the magnetization of their pinned layers in the opposite direction to double the read sense margin. The write operation is also simplified since a current through the HM layer changes the resistances of both MTJs simultaneously. The evaluations include the micromagnetic simulation of the SOT device, the analysis of PVT variations for the read operation on bit-cell level, the estimation of bit-cell area and the simulations of performance and power consumption on array level. The results show that the proposed SOT-MRAM improves the performance and reliability of the read operation and achieves 75% (50%) reduction in bit-cell area compared to 4T-2MTJ SOT-MRAM (2T-2MTJ STT-MRAM), 83.0% reduction in write power consumption and 91.1% reduction in write latency compared to 2T-2MTJ STT-MRAM.

Ultra-low leakage static random access memory design

An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T SRAM cells, leakage power of the proposed cell in hold mode reduced significantly. The stability parameters of the proposed cell are calculated using butterfly method and also N-curve method. Proposed SRAM achieves better write margin with slightly less read margin than 6T SRAM. Proposed technique consumes 790 PW of power in hold mode, which is very less compared to other existing techniques. Therefore, the proposed cell is appropriate for hold mode applications. The simulations are carried out by using Cadence (Virtuoso Schematic and layout editor) tools with GPDK45-nm technology.

Multi-Layered QCA Content-Addressable Memory Cell Using Low-Power Electronic Interaction for AI-Based Data Learning and Retrieval in Quantum Computing Environment.

In this study, we propose a quantum structure of an associative memory cell for effective data learning based on artificial intelligence. For effective learning of related data, content-based retrieval and storage rather than memory address is essential. A content-addressable memory (CAM), which is an efficient memory cell structure for this purpose, in a quantum computing environment, is designed based on quantum-dot cellular automata (QCA). A CAM cell is composed of a memory unit that stores information, a match unit that performs a search, and a structure, using an XOR gate or an XNOR gate in the match unit, that shows good performance. In this study, we designed an XNOR gate with a multilayer structure based on electron interactions and proposed a QCA-based CAM cell using it. The area and time efficiency are verified through a simulation using QCADesigner, and the quantum cost of the proposed XOR gate and CAM cell were reduced by at least 70% and 15%, respectively, when compared to the latest research. In addition, we physically proved the potential energy owing to the interaction between the electrons inside the QCA cell. We also proposed an additional CAM circuit targeting the reduction in energy dissipation that overcomes the best available designs. The simulation and calculation of power dissipation are performed by QCADesigner-E and it is confirmed that more than 27% is reduced.

Gated Attention Recurrent Neural Network: A Deeping Learning Approach for Radar-Based Precipitation Nowcasting

Precipitation nowcasting predicts the future rainfall intensity in local areas in a brief time that impacts directly on human life. In this paper, we express the precipitation nowcasting as a spatiotemporal sequence prediction problem. Predictive learning for a spatiotemporal sequence aims to construct a model of natural spatiotemporal processes to predict the future frames based on historical frames. The spatiotemporal process is an abstraction of some of the spatial things in nature that change with time, and they usually do not change very dramatically. To simplify the model and facilitate the training, we considered that the spatiotemporal process satisfies the generalized Markov properties. The natural spatiotemporal processes are nonlinear and non-stationary in many aspects. The processes are not satisfied with the first-order Markov properties when making predictions, such as the nonlinear movement, expansion, dissipation, and intensity enhancement of echoes. To describe such complex spatiotemporal variations, higher-order Markov models need to be used for the modeling. However, many of the previous models for spatiotemporal prediction constructed were based on first-order Markov properties, losing information on the higher-order variations. Thus, we propose a recurrent neural network which satisfies the multi-order Markov properties to create more accurate spatiotemporal predictions. In this network, the core component is the memory cell structure of the gated attention mechanism, which combines the current input information, extracts the historical state that best matches the existing input from the historical multi-period memory information, and then predicts the future. Through this principle of the gated attention, we could extract the historical state information that is richer and deeper to predict the future and more accurately describe the changing characteristics of motion. The experiments show that our GARNN network captures the spatiotemporal characteristics better and obtains excellent results in the precipitation forecasting with radar echoes.

Gated graph convolutional network based on spatio-temporal semi-variogram for link prediction in dynamic complex network

Link prediction is one of the most important methods to uncover evolving mechanisms of dynamic complex networks. Determining these links raises well-known technical challenges in terms of weak correlation, uncertainty and non-stationary. In this paper, we presented a novel gated graph convolutional network (GCN) based on spatio-temporal semi-variogram (STEM-GCN). It learns spacial and temporal features in order to achieve link prediction in the dynamic networks. In this STEM-GCN model, we first utilized the spatio-temporal semi-variogram to obtain the spacial and temporal correlations from the dynamic networks. Its spacial correlation helped us determine the hyper-parameters of STEM-GCN and speed up its training. The correlation smoothing strategy is also introduced to eliminate the noise through temporal correlation and to improve the accuracy of link prediction. Finally, the network dynamics are captured by propagating the spacial and temporal features between consecutive time steps with stacked memory cell structures. The extensive experiments on real data sets demonstrated the effectiveness of the proposed approach for link prediction in dynamic complex networks.

Investigation of Novel Hybrid Channel Complementary FET Scaling Beyond 3-nm Node From Device to Circuit

Complementary FET (CFET) is a promising candidate for CMOS scaling beyond 3-nm technology node. In this article, a novel hybrid channel CFET (HC-CFET) is proposed, which takes advantage of the vertical structure and simultaneously co-optimizes the preferred high-electron/hole-mobility surface of NMOS/PMOS on one substrate. The flexible combination of nanowires (NWs) and nanosheets (NSs) in the HC-CFET allows NMOS to have (100) channel surface orientation, while PMOS has (110) channel surface orientation without increasing the footprint of CFET pillars. Parasitic-aware device to circuit design-technology co-optimization (DTCO) analysis of the HC-CFET is performed based on advanced TCAD simulation of the device and comprehensive HSPICE simulation with TCAD-calibrated compact model. At the device level, the optimization of the channel surface orientation in the HC-CFET enables both NMOS and PMOS to obtain a current gain of more than 20%. By adjusting the wafer orientation and stacking type, HC-CFET exhibits higher frequency gain and comparable energy consumption in ring oscillator (RO) than multiscreen CFET (MS-CFET) and multibridge CFET (MB-CFET). After fully considering the impact of the stacking type on the static random access memory (SRAM) cell structure, (110) wafer together with n-NW on top of p-NS stack is the preferable approach to manufacture HC-CFET, which helps balance the speed, stability, and area of the SRAM cell.

Novel Nonvolatile Lookup Table Design Based on Voltage-Controlled Spin Orbit Torque Memory

Nonvolatile lookup table (NVLUT) is promising for constructing reconfigurable logic device, such as field programmable gate array (FPGA). In the last decade, there have been extensive studies on constructing novel FPGAs using CMOS technology combined with emerging spintronic devices. However, although spintronic device promises desirable features such as nonvolatility and high area density, its relatively slow switching speed and high power consumption make it quite challenging to use it as a drop-in replacement for static random access memory (SRAM). In this article, we propose a novel nonvolatile NVLUT design, called VC-LUT, based on a voltage controlled spin orbit torque (VC-SOT) device, which utilizes a symmetrical structure of spintronic memory cell and a separated CMOS select tree to enhance operating speed and to reduce power consumption. In our VC-LUT design, two VC-SOT-MTJ devices were placed back-to-back, forming a complementary and symmetrical structure. The VC-LUT circuits are designed and evaluated based on a physics-based VC-SOT-MTJ model and a 40-nm CMOS design-kit. The simulation results show that our proposed design achieves over 98.6% (97.6%) and 69.5% (71.6%) improvement in terms of energy and delay in comparison with the four-input spin transfer torque (STT) [spin orbit torque (SOT)] based counterparts.

A Steep-Slope Phenomenon by Gate Charge Pumping in a MOSFET

A steep-slope phenomenon is experimentally demonstrated and analyzed with a novel FET referred to as a charge pump FET (CP-FET) by using transient switching of the floating gate voltage. It is also analytically modeled and verified by simulation. The CP-FET, which is very similar to a flash memory cell structure composed of a floating gate, was fabricated with 100 % CMOS microfabrication. The transition layer in the CP-FET is analogous to a blocking oxide in a floating gate memory device. Transient switching of the floating gate voltage is achieved by two factors. One is capacitance mismatching between a control gate and the floating gate, which is realized by designing the area of the transition layer to be smaller than that of the floating gate. The other is charge pumping to the floating gate by use of the current flowing through the transition layer.

High resolution front-side visualization of charge stored in EEPROM with scanning nonlinear dielectric microscopy (SNDM)

By exposing floating gates of EEPROM memory cells with frontside sample preparation, scanning nonlinear dielectric microscopy (SNDM) succeeded in reading back the data stored in the memory cells with a 250 nm node size. At an optimized voltage bias of AC = 3 V and DC = 1 V, a clear signal contrast between programmed and erased cells is obtained. The high resolution SNDM signal reveals the details of bowling-pin shape structure of memory cells, providing high confidence in data assignment during forensic applications. Such high resolution also makes SNDM a promising technique for newer generation devices with smaller node size.

(Invited) Some Recent Progress in Ferroelectric Memory Technology

Ferroelectric memory, based on the persistent remnant polarization of certain ferroelectric materials that are switchable by an appropriate applied field, has rekindled tremendous interest ever since the discovery of HfO2-base ferroelectrics [1], and both the 1T1C based ferroelectric random-access memory (FeRAM) and the 1T based ferroelectric-gated field-effect-transistor (FeFET) variety have made significant progress. In this paper, we will review some of the important progress that we have made in both areas, while standing on the shoulders of other previous contributors, starting with the FeRAM technology below.The cell structure of FeRAM is similar to that of a DRAM structure, except that the storage capacitor is replaced by a ferroelectric one, leading to the possibility of nonvolatility without the need for a power-hungry refresh operation of the DRAM. Because of challenges concerning CMOS compatibility, physical thickness scalability, and inability to build 3D ferroelectric capacitors, the traditional perovskite-based ferroelectric materials have prevented the FeRAM cell size from further scaling down beyond the 130-nm technology node, which has confined the current FeRAM products to very limited niche markets [1]. The introduction of HfO2 based ferroelectrics has turned out to be a game changer, as high- quality and scalable ferroelectric capacitors have since been reported [1]. Among various doped and even undoped HfO2 ferroelectric thin films, the HfxZr1-xO2 (HZO) system has attracted extra attention because of its wide composition range and relatively low processing temperature for the formation of the ferroelectric phase (o-phase), making it potentially compatible with Back-End-of-Line (BEOL) process [1]. Here we will present the results of our study on a leading foundry’s BEOL-processed HZO-based ferroelectric capacitors over a wide range of areas (10-2 to 103 µm2) on 12-in wafers [2]. Some critical issues, including wake-up behavior, endurance, retention, size dependence, temperature dependence, and uniformity across the wafers will all be presented and discussed, along with their potential for automotive applications at elevated temperatures. Furthermore, we proposed and demonstrated a novel 6T/4C dual-storage-port NVSRAM by integrating two pairs of HZO-based ferroelectric capacitors onto SRAM cells through the BEOL process, which is promising for numerous IoT applications [3].More coverage of this talk will focus on FeFET cells made by the same foundry using their conventional front-end CMOS process, except for the ferroelectric gate stack of the MOS transistor. It should be noted that the FeFET cell structure was proposed decades ago but failed to commercialize, primarily because of the retention problem associated with the traditional perovskite-based ferroelectric materials [4,5]. The relatively short retention time of those perovskite-based ferroelectric FeFETs , although cannot meet the requirements of nonvolatile memory technology, is more than adequate for DRAM applications. And a 1-T ferroelectric DRAM technology based on FeFETs, named FEDRAM, was proposed [6,7]. One major attraction of the HfO2-based FeFET is its significantly longer retention. In this talk, we will discuss the underlying mechanisms contributing to the retention loss, including the presence of the depolarization field and gate leakage followed by trapping [4]. Moreover, we will present the reason why the FeFET cell based on the ferroelectric HfO2 can achieve better retention time compared with those based on PZT and SBT [8]. While the HfO2-based FeFETs have demonstrated impressive memory retention, they are suffering from limited endurance. We will discuss the causes of such reliability concerns [9]. It will be shown that the endurance failure is mainly attributed to the charge trapping and trap generation in the gate stack, rather than fatigue of polarization in the HfO2 ferroelectric layer. The understanding of the mechanisms behind the retention loss and the endurance issues will help us to formulate possible strategies for further advancing the pathway toward commercialization of the FeFET memory technology. The nearly identical memory cell structure as well as the similar program/erase algorithm between FeFET and NAND Flash memory naturally leads to the concept of 3D ferroelectric memory stacks based on FeFET cells, as proposed by the Yale group [10]. This patented 3D memory technology will also be briefly discussed.[1] T. Mikolajick et al.,MRS Bulletin 43 340(2018) [2] H. Jiang et al., IMW2020 [3] H. Jiang et al., JEDS 8 935(2020) [4] T. P .Ma et al., IEEE EDL 23 386(2002) [5] X. Pan et al., Appl. Phys. Lett. 99 01305 (2011) [6] J.-P. Han et al., Integr. Ferroelect. 27 1053 (1999) [7] K.-H. Kim et al., IEEE EDL 23 82 (2002) [8] N. Gong et al., IEEE EDL 37 (9) 1123 (2016) [9] N. Gong et al., IEEE EDL 39 (1) 15 (2017). [10] Xiao Sun et al., U.S. Patent No. 9,818,848(2017)

INCREASING RADIATION RESISTANCE OF MEMORY DEVICES BASED ON AMORPHOUS SEMICONDUCTORS

A memory cell structure is proposed that uses a Schottky barrier thin film transistor based on an amorphous semiconductor as a junction element, and a chalcogenide glassy semiconductor film as a switching element. A physical storage cell model has been developed. The dependence of the transistor and memory cell parameters on the dose of neutron flux and γ - quanta was investigated. It is shown that when the dose of neutron irradiation is changed, the steepness of the drain-gate characteristic (DGC) decreases by 10% at a dose of the order of 1015 n/s, at the same time, the transfer coefficient of the bipolar n-p-n transistor decreases by 20% already at doses of 1013 n/s, indicating a significant increase in the radiation resistance of the proposed memory cell. In the case of irradiation with γ - quanta in the range up to 2.6 MRad, the steepness of the DGC of the proposed structure changes by only 10%. When used as an isolation element, a field-effect transistor with an insulated gate, the slope of the DGC is reduced by 50%. It is shown that the current of recording information of the proposed structure when changing the dose of γ - quantum flux to 2.6 MRad changes by about 10%, at the same time, in the case of using a field-effect transistor with an isolated cover, the information recording current changes by 50%. The study of the dependence of the gate current on the dose of γ – quanta is showed. When the radiation dose changes from 0 to 2.6 MRad, the gate current changes only by 10%, which indicates the high resistance of the proposed structure to the action of permeable radiation. Also, studies of the dependence of the conductivity of single-crystal semiconductors on the radiation dose ɣ by quanta and neutron flux show that a significant increase in the specific resistivity of AS occurs at doses 2-3 orders of magnitude larger than in the case of single-crystal n-type conductivity semiconductors.

(Invited) Some Recent Progress in Ferroelectric Memory Technology

Ferroelectric memory, based on the persistent remnant polarization of certain ferroelectric materials that are switchable by an appropriate applied field, has rekindled tremendous interest ever since the discovery of HfO2-base ferroelectrics [1], and both the one-transistor-one-capacitor (1T1C) based ferroelectric random-access memory (FeRAM) and the single-transistor (1T) based ferroelectric-gated field-effect-transistor (FeFET) variety have made significant progress. In this paper, we will review some of the important progress that we have made in both areas, while standing on the shoulders of other previous contributors, starting with the FeRAM technology below.The cell structure of FeRAM is similar to that of a DRAM structure, except that the storage capacitor is replaced by a ferroelectric one, leading to the possibility of nonvolatility without the need for a power-hungry refresh operation of the DRAM. Because of challenges concerning CMOS compatibility, physical thickness scalability, and inability to build 3D ferroelectric capacitors, the traditional perovskite-based ferroelectric materials (such as PZT and SBT) have prevented the FeRAM cell size from further scaling down beyond the 130-nm technology node, which has confined the current FeRAM products to very limited niche markets [1]. The introduction of hafnium oxide (HfO2)-based ferroelectrics has turned out to be a game changer, as high-quality and scalable ferroelectric capacitors have since been reported, including TiN/Al:HfO2/TiN-based 3D deep-trench capacitors [1]. Among various doped and even undoped HfO2 ferroelectric thin films, the HfxZr1-xO2 system has attracted extra attention because of its wide composition range and relatively low processing temperature (<= 400 0C), making it potentially compatible with Back-End-of-Line (BEOL) process [1]. Here we will present the results of our study on a leading foundry’s BEOL-processed Hf0.5Zr0.5O2-based ferroelectric capacitors over a wide range of areas (10-2 to 103 µm2) on 12-in wafers. Some critical issues, including wake-up behavior, endurance, retention, size dependence, temperature dependence, and uniformity across the wafers have all been systematically characterized and will be discussed, as well as their potential for automotive applications at elevated temperatures.More coverage of this talk will be focused on FeFET cells made by the same foundry using their conventional front-end CMOS process except for the ferroelectric gate stack of the MOS transistor. It should be noted that the FeFET cell structure was proposed decades ago but failed to commercialize primarily because of the retention problem associated with the traditional perovskite-based ferroelectric materials [2,3]. The relatively short retention time of those perovskite-based ferroelectric FeFETs , although cannot meet the requirements of nonvolatile memory technology, is more than adequate for DRAM applications. And a 1-T ferroelectric DRAM technology based on FeFETs, named FEDRAM, was proposed [4,5]. One major attraction of the HfO2-based FeFET is its significantly longer retention. In this talk, we will discuss the underlying mechanisms contributing to the retention loss, including the presence of the depolarization field and gate leakage followed by trapping [2]. Moreover, we will present the reason why the FeFET cell based on the ferroelectric HfO2 can achieve better retention time compared with those based on PZT and SBT [6]. While the HfO2-based FeFETs have demonstrated impressive memory retention, they are suffering from limited endurance. We will discuss the causes of such reliability concerns [7]. It will be shown that the endurance failure is mainly attributed to the charge trapping and trap generation in the gate stack, rather than fatigue of polarization in the HfO2 ferroelectric layer. The understanding of the mechanisms behind the retention loss and the endurance issues will help us to formulate possible strategies for further advancing the pathway toward commercialization of the FeFET memory technology.The nearly identical memory cell structure as well as the similar program/erase algorithm between FeFET and NAND-Flash memory naturally leads to the concept of 3D ferroelectric memory stacks based on FeFET cells, as proposed by the Yale group [8]. This patented 3D memory technology will also be briefly discussed.This work was supported by the National Science Foundation (NSF) under Award No: 1609162.

Radiation-Resistant Memory Device Based on Chalcogenide Glassy Semiconductor

A memory cell structure is proposed that uses a Schottky barrier thin film transistor based on an amorphous semiconductor as a junction element, and a chalcogenide glassy semiconductor film as a switching element. A physical storage cell model has been developed. The dependence of the transistor and memory cell parameters on the dose of neutron flux and γ - quanta was investigated. It is shown that when the dose of neutron irradiation is changed, the steepness of the drain-gate characteristic (DGC) decreases by 10% at a dose of the order of 1015 n/s, at the same time, the transfer coefficient of the bipolar n-p-n transistor decreases by 20% already at doses of 1013 n/s, indicating a significant increase in the radiation resistance of the proposed memory cell. In the case of irradiation with γ - quanta in the range up to 2.6 Mrad, the steepness of the DGC of the proposed structure changes by only 10%. When used as an isolation element, a field-effect transistor with an insulated gate, the slope of the DGC is reduced by 50%, that it is bad result. It is shown that the current of recording information of the proposed structure when changing the dose of γ - quantum flux to 2.6 Mrad changes by about 10%, at the same time, in the case of using a field-effect transistor with an isolated cover, the information recording current changes by 50%. The study of the dependence of the gate current on the dose of γ – quanta is showed. When the radiation dose changes from 0 to 2.6 Mrad, the gate current changes only by 10%, which indicates the high resistance of the proposed structure to the action of permeable radiation.

A New High Selectivity Acidic Slurry for Chemical Mechanical Planarization of Carbon-Doped Ge2Sb2Te5 Film

During the industrial application of the new phase change memory material carbon-doped Ge2Sb2Te5 (GSTC), it is necessary to perform planarization for the confined memory cell structure through the chemical mechanical polishing (CMP) process. The goal of CMP is to acquire a high material removal rate and selectivity while ensuring that the polished surface is free of scratches and corrosion pits. A new acidic slurry added with potassium persulfate (OXONE) as an oxidizer was developed. The acidic slurry added with 5000 ppm OXONE has a amorphous GSTC film material removal rate of 5200 Å min−1, a high selectivity between GSTC and Si3N4 films of 950:1, and no corrosion-induced pit. In order to clarify the mechanism of GSTC CMP with OXONE, the Energy Dispersive Spectrometer, potentiodynamic polarization curve and X-ray photoelectron spectroscope were adopted to analyze the surface of GSTC. It is found that the chemical reaction mechanism is significantly different from that of hydrogen peroxide (H2O2). Finally, the mechanism of GSTC during the CMP with OXONE in the acidic slurry is depicted.

Improving Utilization and Life-Span in Parallel Aware MLC-Based SSD Using Virtual Blocks

FTL (Flash Translation Layer) is a memory block controller that manages the challenges of a data storage system based on flash memory technology. The design of internal parallelism in MLC-based SSDs with virtual blocks resulted in various challenges and due to the physical structure of flash memory cells based on MLC technology, it is possible to write a new page in a data block at the address after the last page is written. In parallel-based SSD design based on virtual blocks, some writes create unusable pages at the memory space, and these created holes reduce memory efficiency; consequently, it reduces the life-time of memory blocks by creating more operations, and accelerates garbage collection and merging operations. The proposed FTL offers three steps to address this constraint. Firstly, an idea was proposed to prevent costly transitions and to distribute data more evenly at memory blocks (wear leveling). Secondly, the unused holes created in virtual blocks became much fewer resulting in increased utilization of memory space. At last, a policy was proposed to prevent update blocks (log blocks) from being blocked and to postpone the merging and garbage collection by which the memory lifetime increases significantly. Simulation results showed that the number of unused erased pages and the number of extra write operations decreased up to 23% and 17%, respectively. In addition, the number of invalid released pages increased up to 21% in the proposed FTL, and the speed of I/O executions to 3%.

Area Efficient High Through-put Dual Heavy Metal Multi-Level Cell SOT-MRAM

This paper proposes a novel multi-level cell spin-orbit torque magnetic random-access memory (MLC SOT-MRAM) cell structure and validates its functionality and performance through simulation. The proposed memory cell comprises two uniform magnetic tunnel junctions (MTJs) that can be programmed separately by the energy efficient SOT technology through two different heavy metal electrodes. This permit employing both single and dual port architectures. The uniform cross-sectional area of the in-series MTJs stack simplifies the fabrication process. In addition, the cell structure requires only four terminals to successfully read and write the two bits. This allows accessing the two bits with only three access transistors, which achieves 25% smaller 1-bit effective area compared to the conventional single level cell (SLC) SOT-MRAM that requires four transistors. Simulation results based on an approximated dynamic model shows it offers nearly similar write energy consumption compared to the conventional SOT-MRAM.

A survey on LSTM memristive neural network architectures and applications

The recurrent neural networks (RNN) found to be an effective tool for approximating dynamic systems dealing with time and order dependent data such as video, audio and others. Long short-term memory (LSTM) is a recurrent neural network with a state memory and multilayer cell structure. Hardware acceleration of LSTM using memristor circuit is an emerging topic of study. In this work, we look at history and reasons why LSTM neural network has been developed. We provide a tutorial survey on the existing LSTM methods and highlight the recent developments in memristive LSTM architectures.