Investigation of Novel Hybrid Channel Complementary FET Scaling Beyond 3-nm Node From Device to Circuit

Abstract

Complementary FET (CFET) is a promising candidate for CMOS scaling beyond 3-nm technology node. In this article, a novel hybrid channel CFET (HC-CFET) is proposed, which takes advantage of the vertical structure and simultaneously co-optimizes the preferred high-electron/hole-mobility surface of NMOS/PMOS on one substrate. The flexible combination of nanowires (NWs) and nanosheets (NSs) in the HC-CFET allows NMOS to have (100) channel surface orientation, while PMOS has (110) channel surface orientation without increasing the footprint of CFET pillars. Parasitic-aware device to circuit design-technology co-optimization (DTCO) analysis of the HC-CFET is performed based on advanced TCAD simulation of the device and comprehensive HSPICE simulation with TCAD-calibrated compact model. At the device level, the optimization of the channel surface orientation in the HC-CFET enables both NMOS and PMOS to obtain a current gain of more than 20%. By adjusting the wafer orientation and stacking type, HC-CFET exhibits higher frequency gain and comparable energy consumption in ring oscillator (RO) than multiscreen CFET (MS-CFET) and multibridge CFET (MB-CFET). After fully considering the impact of the stacking type on the static random access memory (SRAM) cell structure, (110) wafer together with n-NW on top of p-NS stack is the preferable approach to manufacture HC-CFET, which helps balance the speed, stability, and area of the SRAM cell.