Structure Of Carry Select Adder Research Articles

Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder

We have proposed a modified Carry Select Adder (CSLA) structure which uses a parallel prefix structure with Binary to Excess – 1 converter (BEC). The proposed adder has been compared with Conventional, BEC, Brent – Kung (BK), Ladner – Fischer (LF) and Kogge – Stone (KS) based CSLA in terms of area, power consumption and performance. The proposed CSLA shows a significant decrease in the area and power compared to KS based CSLA. Particularly, the proposed CSLA structure exhibit significant improvement in speed by 54.41%, 7.95%, 7.82% to Conventional CSLA, 65.75%, 24.65%, 21.61% to BEC-CSLA, 50.79%, 13.83%, 9.30% to BK-CSLA, 43.12%, 8.99%, 5.35% to LF-CSLA, 44.64%, 10.50%, 6.30% to KS-CSLA for 4 bit, 8 bit and 16 bit respectively. All the CSLA structures are designed using Verilog HDL, simulations and synthesis have been performed in Cadence tool using 0.18 µm CMOS technology.

An efficient architecture for carry select adder

PurposeAdders play a vital role in almost all digital designs, as all four arithmetic operations can be confined within addition. Hence, area and power optimization of the adders will result in overall circuit optimization. Being the fastest adder, the carry select adder (CSLA) gains higher importance among the different adder styles. However, it suffers from the drawback of increased power and area. The implementation of CSLA in digital circuits requires lots of study for optimization. Hence, to overcome this problem, various improvements were made to the CSLA structure to reduce area and, consequently, reduce power. Among these, modified CSLAs show a significant improvement, as they utilize a binary excess-1 code (BEC) to replace the add-one circuit.Design/methodology/approachThis paper presents further enhancement in the modified CSLA by proposing a decision-based CSLA, which activates BEC on demand. This leads to reduced switching activity. The performance of the proposal is done by analyzing and comparing it with different adders. The comparison is done on the basis of three performance parameters: area, speed and power consumption. This is done by implementing the architecture on Xilinx Virtex5 XC5VLX30 in Verilog environment and is synthesized using Cadence® RTL Compiler® using TSMC 180-nm CMOS cell library.FindingsOptimization of power, area and increasing the speed of operation are the three main areas of research in very-large-scale integration (VLSI) design for portable devices. As adders are the most fundamental units for any VLSI design, optimization at the adder level has a huge impact on the overall circuit. The modified CSLA has a BEC which continuously switches irrespective of the previous carry bit generated. The unwanted switching results in excess power consumption while also introducing additional delay. Hence, the author has proposed a decider circuit to avoid this excess switching activity. This allows switching of the BEC only when a previous carry is generated. The modified CSLA is based on the ripple carry adder, while the decider-based CSLA utilizes a carry look-ahead adder. This makes a decider-based CSLA faster while utilizing less area and power consumption when compared to the modified CSLA.Originality/valueThe efficiency of the proposed decider-based CSLA has been verified using Cadence RTL Compiler using TSMC 180-nm CMOS cell library and has been found to have 17 per cent power and 11.57 per cent area optimization when compared to the modified CSLA, while maintaining operating frequency.

An energy and area efficient yet high-speed square-root carry select adder structure

In this paper, we propose a modified carry select adder (CSLA) structure which is more power/energy and area-efficient compared to the existing CSLAs. The higher efficiency is achieved by modifying the logic formulations of the carry generation and selection (CGS) scheme and merging all of its redundant logic operations in the carry generation (CG) and carry selection (CS) units of the CGS-based CSLA (CGS-CSLA) structure. This leads to a simplified structure. Next, the proposed CSLA structure is employed to design efficient square-root CSLA (SQRT-CSLA) structure. The efficiency of the proposed SQRT-CSLA is investigated by comparing its speed, power, energy, and area parameters with those of some other SQRT-CSLA structures, including conventional SQRT-CSLA, binary to excess-1 converter, common Boolean logic, and the CGS-based SQRT-CSLA structures. The investigation, which is performed using HSPICE simulations based on a 45nm bulk CMOS technology, includes 8, 16, 32, and 64-bit adder structures. The impact of voltage scaling on the efficiency of the proposed structure is also studied by changing the supply voltage levels from the near-threshold voltage to the nominal supply voltage. Simulation results reveal that the proposed SQRT-CSLA provides, at least, 14%, 14%, and 15% lower energy, energy-delay product, and area-delay product, respectively, compared to those of the CGS-based SQRT-CSLA structure, averaged over the supply voltage and bit length.

Low Power, Area-Efficient and High Speed Fast Adder for Processing Element

In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate - level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Modified Carry select adder (MCSLA), Regular Square Root CSLA (SQRT CSLA), Modified SQRT CSLA and Proposed SQRT CSLA in terms of area, delay and power consumption. The result analysis shows that the proposed structure is better than the conventional CSLA.

A DESIGN OF AREA AND POWER EFFICIENT HIGH SPEED DATA PATH LOGIC SYSTEM

Carry Select Adder (CSLA) is one of the fastest adders use in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18- m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

Design and Simulation of Low Power and Area Efficient SQRT Carry Select Adder with Modified Binary to Excess-1 Converter

In the design of Integrated circuits, area occupancy and power consumption plays a vital role because of increasing necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient transistor level modification of EX-OR gate used in BEC-1 converter to significantly reduce the area and power of the CSLA. Based on this modification 4, 8, 16-bit SQRT CSLA architecture have been developed and compared with the SQRT CSLA architecture using AND, OR, INVERTER (AOI) implementation of EX- OR gate used in BEC-1 converter. The proposed SQRT CSLA is designed in 130 nm technology. The proposed design has reduced area and power as compared with the SQRT CSLA using ordinary BEC-1 converter. This work evaluates the performance of the proposed designs in terms of area and power. The results analysis shows that the proposed SQRT CSLA structure is better than the regular SQRT CSLA.

Modified 16-b Square-root Low Power Area Efficient Carry Select Adder

Due to acceptance of the portable system with fast growth of power density in the integrated circuits, the power dissipation and the performance is considered while the system is designed. The main goal of the VLSI design is to design the adders in more efficient way. By that way the Carry Select Adder (CSLA) is an adder designed, which computes n+1 bit sum of two n bit numbers. In this study Modified 16-b SQRT with Modified Area efficient CSLA is proposed. From the design of Modified Area Efficient CSLA it is experiential that there is an option of reducing the area more and consumes low power when compared with Regular CSLA. Modified Area Efficient CSLA (MA-CSLA) utilizes BEC which reduces the area more and the total gate count is also gets condensed. The proposed study makes use of a simple and well-organized gate-level alteration to considerably reduce the area and power of the CSLA. By the support of alteration 8-, 16-, 32- and 64-b, respectively Square-Root CSLA (SQRT CSLA) model have been evolved and evaluated with the regular SQRT CSLA model. This study estimates the performance of the proposed designs in terms of delay, area and power. The results analysis shows that the proposed Modified Area Efficient CSLA structure is better than the regular SQRT CSLA.

MINIATURE IMPROVED CARRY SELECT ADDER WITH ADVANCE FEATURES AND POWER REQUIREMENTS

In most of the data processing processors to perform arithmetic functions Carry Select Adder (CSLA) is used as this is one of the fastest adders. In order to increase the overall efficiency of the processor we can reduce the area and power consumption of the CSLA of processors. Based on this premise we can modify the regular SQRT CSLA architecture as 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

FPGA Implementation of Area Efficient and Delay Optimized 32-Bit SQRT CSLA with First Addition Logic

Binary addition is a fundamental operation in most digital circuits. There are a variety of adders, each has certain performance. Parallel adders are used for fast binary addition which plays a crucial impersonation in majority of digital circuit designs including digital signal processors (DSP) and microprocessor data path unit. In this project we implement the parallel adder 32-bit SQRT CSLA(square root carry select adder) with BEC logic and compare them to the simple ripple carry adder(RCA),carry look ahead adder(CLA) & carry select adder(CSLA). To reduce the area and delay of n-bit CSLA, n-bit SQRT CSLA with BEC-1 logic was designed. Since CSLA is area consuming because it consists of dual RCA in structure. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. So as to achieve the same an efficient gate-level modification would be implemented to vitally reduce the delay of the CSLA. 32bit SQRT CSLA with BEC-1logic is already designed which reduces the area of corresponding CSLA. But while performing area reduction and power reduction it is found that there is an increase in the delay. So in this project we put forward the structure of square root CSLA (SQRT CSLA) using “first addition logic circuit(FAL)” for 32-bit instead of BEC-1 logic circuit. The performance in terms of area, delay and utilization of power are calculated for SQRT CSLA with FAL and are compared with existing CSLA, SQRT CSLA and SQRT CSLA with BEC-1 logic.

Low-Power and Area-Efficient Carry Select Adder

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

A new addition scheme and fast scaling factor compensation methods for CORDIC algorithms

As CORDIC algorithms attract more and more attention in elementary function evaluation and signal processing applications, the problem of their VLSI realization has drawn considerable interest. In this work we present speed enhancement techniques for these types of algorithms, covering algorithmic and implementation issues. We discuss speed limiting issues, namely addition techniques, appropriate number systems and scaling factor compensation with special emphasis on low latency time. A new carry-select adder structure will be presented that offers an excellent tradeoff between speed and VLSI chip area. With two scaling factor compensation schemes the fastest or most area economical CORDIC implementations are feasible. Also, the close relationship between SRT division and the new redundant CORDIC algorithms will be demonstrated.