Structural Adders Research Articles

Multiplication and Accumulation Co-Optimization for Low Complexity FIR Filter Implementation

In multiplierless finite impulse response (FIR) filters, the product accumulation block (PAB) could be the major contributor to hardware complexity, especially for high-order filters. In this paper, an optimization scheme where the constant multiplication block and the PAB are jointly optimized at the bit-level is proposed to minimize the hardware complexity. In the proposed joint optimization, the multiple constant multiplications (MCM) block is rearranged into several MCM sub-blocks. The products are summed locally before accumulation to reduce the word-length of the structural adders. It is shown that the symmetric property of linear phase FIR filters can be utilized in some cases to further reduce the complexity of the constant multiplications. Quantitative analyses are also presented to study the relationship between the optimum group size and the coefficient values as well as the filter orders. It is shown that there is no fixed optimum structure for filters with different coefficient word-lengths and filter orders, and each filter needs to be optimized specifically to achieve the minimum hardware complexity. Implementation results are presented to validate the effectiveness of the proposed method.

High Speed FIR Filter Design using Multiplier Sharing and Sub-Expression Elimination Method

FIR filter is the basic filter used in many DSP applications because of its linear phase , stability , low cost and simple structure . Designing a high- speed and hardware efficient FIR filter is a very difficult task as the complexity increases with the filter order .In most Application the higher order filters are required but the memory usage of filter increases exponentially with the order of the filter using multipliers occupy a large chip area and need more access time. So the design and implementation of highly efficient look up table (LUT) based circuit for the implementation using DA Algorithm increases the speed. Multiplier sharing and sub-expression elimination methods are proposed to optimize the Structural adders. These methods split the structural adders into smaller adder blocks to reduce the delay. In order to reduce the complexity of structural adders round-off can be performed at the cost of sacrificing precision of the filter.

Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters

Finite-impulse response filters are widely used in digital signal processing applications. Prodigious research in the past two decades has substantially reduced the implementation cost of the multiple constant multiplication blocks. Further area and power consumption savings are stagnated by the structural adders and registers in the tap delay-and-accumulate line, which unfortunately dominate the overall hardware cost of FIR filter and are difficult to minimize by existing resource sharing approaches. Retiming or relocating the structural adders and registers can improve merely the throughput. To close the area-power efficiency gap, we reformulate the filter coefficient synthesis problem to explore the design space for the tap delay-and accumulate line by bisecting at some tap position. An efficient Genetic Algorithm is proposed to solve this integer programming problem at quadratic computational complexity by refining the search space for finding an optimized solution to fulfill the frequency response specifications. Field programmable gate array and application specific integrated circuit logic synthesis results from twelve benchmark filter specifications showed that the average area and power consumptions of the solutions generated by our proposed algorithm have been reduced by up to 26.8% and 27.5% respectively, in comparison with the solutions obtained by existing design methods.

Novel Structure for Area-Efficient Implementation of FIR Filters

It is observed that in multiplierless implementation of transposed direct form finite impulse response (FIR) filters, the adders in the product-accumulation block, which are called structural adders (SAs), contribute the major part of the overall logic complexity. A novel FIR filter structure is therefore proposed to reduce the hardware complexity of the product-accumulation block. In the proposed structure, half of the long word-length SAs are replaced by adders, which are called pre-SAs, which have a relatively shorter word length. The filter coefficients are carefully grouped to take advantage of the symmetric impulse response of linear phase FIR filters. Analysis and experimental results show that the overall area complexity and power consumption can be reduced at the expense of negligible delay overhead. The average area and power reduction over existing techniques can be as much as 23.8% and 25.4%. The overall area-delay performance and power-delay performance of the proposed implementation is superior to existing techniques.

Design of Low-Power Multiplierless Linear-Phase FIR Filters

In the design of multiplierless finite impulse response (FIR) filters, tremendous efforts have been made to reduce the number of adders of the multiplier block for the reduction of overall chip area and power consumption. However, fewer in the multiplier block do not necessarily lead to lower power consumption, since the structural adders dominate the power consumption of an FIR filter circuit. In this paper, we propose a power-oriented optimization method for linear phase FIR filters. In the proposed algorithm, the power index, which is the average adder depth of the structural adders, is used as the optimization objective in the discrete coefficients search. A gate-level simulation of benchmark filters shows that the proposed technique designs filters consuming less power than those obtained by the best available algorithms, which aim to minimize the number of adders. The power savings over existing designs can be as much as 19.6%.

Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters

Most of the research on the implementation of finite impulse response (FIR) filter so far focuses on the optimization of the multiple constant multiplication (MCM) block. But it is observed that the product-accumulation section often contributes the major part of the critical path, such that the timing optimization of MCM block does not impact significantly on the overall speedup of the FIR filters. In this paper, a precise analysis and optimization of critical path for transposed direct from (TDF) FIR filters is proposed. The delay increment introduced by structural adders is estimated by comparing the delay of a tap and the corresponding delay of the coefficient multiplication only. Based on that, a novel implementation of the product-accumulation section of FIR filters is proposed by retiming the existing delays into the structural adders. It is also shown that the structural adders can be integrated with the MCM block and retimed together for further reduction of critical path. By using the proposed method, the increment of delay caused by the structural adders can be either completely eliminated or significantly reduced. Experimental results show that the critical path delay can be significantly reduced at the cost of very small area overhead. The overall area-delay performance and power-delay performance of the proposed method are superior to the existing methods.

Design of Digital FIR Filter Based on MCMAT for 12 bit ALU using DADDA & WALLACE Tree Multiplier

Over a period of time, there are different types of multipliers used to minimize cost of constructive parameters in digital FIR filter design in different forms. In these multipliers truncated multiplier design play’s an essential role. Due to multiple adders and delay elements the circuit in transpose form occupies more area and consumes power. In the proposed method effectiveness in different parameters are achieved with low cost, high speed and effective results are done by faithfully rounded truncated multipliers with operations of carry save adder. Direct form of FIR filter utilizes based on MCMAT for multiplication and accumulation operations; it will reduce the area by decreasing the number of different components like structural adders and registers. By using MCMAT operation in the digital FIR filters, optimal results can be obtained in terms of power and area specifications. The proposed 12 bit Arithmetic and Logic Unit is designed along with MCMAT based digital FIR filter for reducing area and increasing speed in real time applications.