Abstract
Over a period of time, there are different types of multipliers used to minimize cost of constructive parameters in digital FIR filter design in different forms. In these multipliers truncated multiplier design play’s an essential role. Due to multiple adders and delay elements the circuit in transpose form occupies more area and consumes power. In the proposed method effectiveness in different parameters are achieved with low cost, high speed and effective results are done by faithfully rounded truncated multipliers with operations of carry save adder. Direct form of FIR filter utilizes based on MCMAT for multiplication and accumulation operations; it will reduce the area by decreasing the number of different components like structural adders and registers. By using MCMAT operation in the digital FIR filters, optimal results can be obtained in terms of power and area specifications. The proposed 12 bit Arithmetic and Logic Unit is designed along with MCMAT based digital FIR filter for reducing area and increasing speed in real time applications.
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