Novel Structure for Area-Efficient Implementation of FIR Filters

Abstract

It is observed that in multiplierless implementation of transposed direct form finite impulse response (FIR) filters, the adders in the product-accumulation block, which are called structural adders (SAs), contribute the major part of the overall logic complexity. A novel FIR filter structure is therefore proposed to reduce the hardware complexity of the product-accumulation block. In the proposed structure, half of the long word-length SAs are replaced by adders, which are called pre-SAs, which have a relatively shorter word length. The filter coefficients are carefully grouped to take advantage of the symmetric impulse response of linear phase FIR filters. Analysis and experimental results show that the overall area complexity and power consumption can be reduced at the expense of negligible delay overhead. The average area and power reduction over existing techniques can be as much as 23.8% and 25.4%. The overall area-delay performance and power-delay performance of the proposed implementation is superior to existing techniques.