Stress Of Through Silicon Via Research Articles

Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs

In this paper, we study the impact of through-silicon-via (TSV) and shallow trench isolation (STI) stress on the timing variations of 3-D IC. We also propose the first systematic TSV-STI-stress-aware timing analysis and show how to optimize layouts for better performance. First, we generate a stress contour map with an analytical radial stress model for TSV. We also develop a stress model for STI from finite element analysis results. Then, depending on geometric relation between TSVs, STI, and transistors, the tensile and compressive stresses are converted to hole and electron mobility variations. Mobility-variation-aware cell library and netlist are generated and incorporated into an industrial engine for timing analysis of 3-D IC. We observe that TSV stress and STI stress interact with each other, and rise and fall time react differently to stress and relative locations with respect to both TSVs and STIs. Overall, TSV-STI-stress-induced timing variations can be as much as ±15% at the cell level. Thus, as an application to layout optimization, we exploit the stress-induced mobility enhancement to improve performance of 3-D ICs. We show that stress-aware layout perturbation could reduce cell delay by up to 23.37% and critical path delay by 6.67% in our test case.

Study on Cu Protrusion of Through-Silicon Via

The through-silicon via (TSV) approach is essential for 3-D integrated circuit (3-DIC) packaging technology. TSV fabrication process, however, is still facing several challenges. One of the widely known challenges is via protrusion. Annealing a TSV wafer puts the copper (Cu) TSVs under high stress and may form a protrusion where the Cu is forced out of the blind TSV. This phenomenon occurs because the large mismatch in the coefficient of thermal expansion between Cu via and silicon (Si) surrounding it. Cu protrusion can lead to crack or delamination of the back-end-of-line, thus, it is a risky threat to the metal layer interconnect. Experiments are conducted to characterize the protrusion using several techniques. Scanning electron microscopes and atomic force microscopes are used to observe the protrusion shape and measure the height. An electron backscatter diffraction technique is implemented to study the grain size distribution and evolution inside Cu vias. For the experiment, arrays of 5- $\mu{\rm m}$ TSVs are fabricated and annealed in nitrogen gas environment in different temperatures. In this paper, finite element analysis (FEA) is carried out to study the Cu protrusion under different annealing conditions. Correlation between numerical results and experimental data is then carried out. Based on the verified FEA methodology, several parametric studies are then conducted, including the effect of via diameter, depth, pitch, annealing temperature, and duration on Cu protrusion and TSV stress. The simulation results help to understand and solve the key problem in TSV fabrication process and reliability challenge.

Thermo-mechanical Stress of Underfilled 3D IC Packaging

In recent years, there has been a dramatic proliferation of research concerned with electronic products because of more various functions are integrate into the device and product's size has become smaller. As a result of these functional requirements, through silicon via (TSV) was investigated, this are getting considerable attentions not only from reducing the packaging size but also from shortening the interconnection's distance that can achieve the effect of enhancing signal transmission. TSVs are the vertical hole through the stacked IC, and they are also responsible for transferring signals between the ICs. Thus, they can improve the time delay of the signal transduction and allow better electrical performance than stacked ICs with wire bonding technology. However, a review of the literature indicates that electronic components will be affected easily by environmental factors such as humidity, pressure, and temperature. In general, the stacked ICs with TSV structure is easily affected by temperature changes than others factors since each material have different deformation. In very recently, the stacked IC packaging has been primarily concerned with thermo-mechanical loadings than traditional single IC packaging, which leads some problems such as via cracking, die cracking and interfacial delamination and so on. The above problems not only affect the performance of the device but also lead the device fail. Hence, most of the studies [1–9] are focus on discussing thermal mechanical loading with simulation method. Some of them discuss the relationship between the TSV shape and the stresses [4, 5]. In addition, most of people just build local TSV structure to do their research [4–9]. Although it can save more time but it also increase the error percentage with real situation. And this paper build the three dimensional four layers stacked IC packaging model from Hsieh [1]'s paper which can more close to real situation. And setting the structure to be simulated from the temperature 150°C to −50°C which is as retreat temperature. This paper use ANSYS software which is based on finite element theory in order to reduce time used and save money, as finite element simulation can provide results more quickly and cheaply than experiments. Moreover, the research mainly analyzes the average value of maximum von Mises stress in TSVs and chips. Besides, this paper will sort out geometries and material properties which will serious affect von Mises stress value by design of experiments (DoE) analysis. Through the DoE analysis, the critical factors are selected as main design factors to reduce the von Mises stresses. This study can provide the significant information to effectively design the products and increase the reliability. This information can also eliminate the testing time.

Application of Low-k Liner for Stress and Capacitance Control in Cu-TSV

Through silicon via (TSV) is commonly fabricated by high aspect ratio deep silicon etching, lining with dielectric layer for electrical isolation and super-conformal filing with copper. It has been reported that Cu-TSV can exert thermo-mechanical stress on Si due to coefficient of thermal expansion (CTE) mismatch. This stress can result in undesired device mobility variation and structural reliability. In addition, TSV parasitic capacitance has the most predominant impact on the circuit operation. It is therefore imperative to reduce the TSV stress and capacitance. One solution is to use low-k dielectric as the liner since it has much lower elastic modulus and effective permittivity. In this work, low-k dielectric is successfully integrated in TSV as a liner. The implications on TSV stress, capacitance and leakage current are discussed. Due to its smaller elastic modulus (~7.2 GPa), the selected low-k carbon-doped oxide acts as a compliant layer to cushion the Cu-TSV stress on the Si compared with conventional oxide (75 GPa) by plasma enhanced chemical vapor deposition. This effectively reduces the near-surface compressive stress in Si by >25% compared with the conventional liner which is more rigid. Since the low-k liner has an effective dielectric constant of ~2.8, it is found that the integration of the low-k liner reduces the TSV capacitance by ~26% as compared with the conventional oxide liner. In summary, this work has provided evidence of the technical merits of a low-k material to mitigate the undesired Cu-TSV induced stress in the surrounding Si and the related parasitic capacitance.

Measurement and analysis of thermal stresses in 3D integrated structures containing through-silicon-vias

Three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective approach to overcome the wiring limit beyond the 32nm technology node. Due to the mismatch of thermal expansion between the via material and Si, thermal stresses ubiquitously exist in the integrated 3-D structures. The thermal stresses can be significant to raise serious reliability issues, such as TSV extrusion and mobility degradation of logic devices. To understand the characteristics of the thermal stresses in TSVs, experimental measurements and numerical analysis are presented in this work. A precision wafer curvature technique was used together with micro-Raman spectroscopy to form a complementary approach to characterize the deformation and stresses in the TSV structures. The microstructures of the Cu vias were analyzed to provide insights to the deformation mechanisms. Guided by the experimental observations, finite element analysis was performed to analyze the thermal stresses taking into account the elastic anisotropy of Si and the plasticity of Cu. It was found that plastic deformation is localized within the Cu vias near the via/Si interface and may play an important role in TSV extrusion. Finally, the effect of thermal stresses on carrier mobility was investigated to evaluate the keep-out zone (KOZ) for logic devices near the TSVs.

Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package

Thermal conduction and mechanical stresses in through silicon via (TSV) structures in three dimensional system in package (3D SiP) under device operation condition were discussed. A large scale simulator, ADVENTURECluster® based on finite element method (FEM) was used to simulate the effects of voids formed inside Cu TSVs on the thermal conduction and mechanical stresses in the TSV structure. The thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses in the TSV structure in 3D SiP were carried out under thermal condition due to power ON/OFF of device. In case that void was not present inside the TSV, the stresses in TSV were close to the hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. Maximum principal stress of the Si chip in the TSV structure for the case without voids was lower than that of the bending strength of silicon. However, the level of the stresses in the Si chips should not be negligible for damages to Si chips. In case that void was present inside the TSV, stress concentration was occurred around the void in the TSV. The magnitude of the equivalent stress in the TSV was lower than the yield stress of copper. The magnitude of the maximum principal stress of the Si chip was lower than that of the bending strength of silicon. However, its level should not be negligible for damages to TSVs and Si chips. The stress on inner surfaces of Si chip was slightly reduced due to the presence of a void in the TSV.

Reliability Assessment of Through-Silicon Vias in Multi-Die Stack Packages

A thermo-mechanical reliability study of through-silicon vias (TSVs) is presented in this paper. TSVs are used to interconnect stacked dies to achieve 3-D packages. As the core of the TSV contains high coefficient of thermal expansion (CTE) copper surrounded by low-CTE SiO2 and Si materials, the thermo-mechanical reliability of TSVs is a concern. When dies with such TSVs are stacked and packaged, the presence of additional structures and associated materials could introduce different thermo-mechanical concerns compared with free-standing wafers. This paper presents 3-D finite-element models for studying the thermo-mechanical stresses in TSVs in free-standing wafers and in stacked dies, which are packaged. Warpage measurements have been used to validate the finite-element modeling approach. The results from the finite-element models show that the TSV stresses in a packaging configuration are typically lower than the TSV stresses in a free-standing wafer configuration. In addition, it is seen that the microbumps connecting adjacent dies experience high magnitude of inelastic strain, indicating that such locations are of reliability concern.

Characterization of thermal stresses in through-silicon vias for three-dimensional interconnects by bending beam technique

Through-silicon via is a critical element for three-dimensional (3D) integration of devices in multilevel stack structures. Thermally induced stresses in through-silicon vias (TSVs) have raised serious concerns over mechanical and electrical reliability in 3D technology. An experimental technique is presented to characterize thermal stresses in TSVs during thermal cycling based on curvature measurements of bending beam specimens. Focused ion beam and electron backscattering diffraction analyses reveal significant grain growth in copper vias, which is correlated with stress relaxation during the first cycle. Finite element analysis is performed to determine the stress distribution and the effect of localized plasticity and to account for TSV extrusion observed during annealing.

Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits

Through-silicon via (TSV) has been used for 3-dimentional integrated circuits. Mechanical stresses in Cu and Si around the TSV were measured using synchrotron X-ray microdiffraction. The hydrostatic stress in Cu TSV went from high tensile of 234MPa in the as-fabricated state, to −196MPa (compressive) during thermal annealing (in situ measurement), to 167MPa in the post-annealed state. Due to this stress, the keep-away distance in Si was determined to be about 17μm. Our results suggest that Cu stress may lead to reliability as well as integration issues, while Si stress may lead to device performance concerns.

Applying x-ray microscopy and finite element modeling to identify the mechanism of stress-assisted void growth in through-silicon vias

Fabricating through-silicon vias (TSVs) is challenging, especially for conformally filled TSVs, often hampered by the seam line and void inside the TSVs. Stress-assisted void growth in TSVs has been studied by finite element stress modeling and x-ray computed tomography (XCT). Because x-ray imaging does not require TSVs to be physically cross-sectioned, the same TSV can be imaged before and after annealing. Using 8 keV laboratory-based XCT, voids formed during copper electroplating are observed in as-deposited samples and void growth is observed at the void location after annealing. We hypothesize that the mechanism generating voids is hydrostatic stress-assisted void growth. Stresses in a copper-filled TSV with a pre-existing void were simulated by finite element methods. The peaks of the hydrostatic stress and its gradient are shown to be around the edge of the void. Comparing simulated results and experimental data shows that void growth in TSVs is stress-assisted: vacancies diffuse and coalesce at the void as a result of the hydrostatic stress gradient.

Thermo-Mechanical Response of Thru-Silicon Vias Under Local Thermal Transients Using Experimentally Validated Finite Element Models

Significant research has focused on the reliability of through-silicon-vias (TSVs) under conventional uniform thermal loading conditions such as accelerated thermal cycling (0–100 °C) or deep thermal cycling (−40–125 °C). This study analyzes the thermomechanical behavior of TSVs in 3D packages undergoing rapid local temperature fluctuations, as would be experienced in actual operation. A global/local finite element model is used to analyze the TSV behavior at various distances from the thermal fluctuation site. Transient thermal measurements, warpage and in-plane deformation measurements, as well as micro-Raman spectroscopy measurements are used to validate the model. The results reveal that the short term local temperature transients have minimal impact on the TSV stress state regardless of TSV location, implying that global package- induced stresses dominate.

Strain Gradient Finite Element Analysis of Size Dependence of Thermal Stresses in Through-Silicon Vias (TSVs)

Through-Silicon Vias (TSVs) technology, which is widely used in three-dimensional (3D) Microsystems packaging, has been investigated by using a strain gradient finite element method (FEM). A thermomechanical strain gradient constitutive law was embedded into the commercial software ABAQUS to consider the size dependence of thermal stresses in TSVs. Our numerical results show that when both thicknesses of SiO2 dielectric layer and Si substrate are kept to a constant, for a given via depth/radius ratio, the Mises stress decreases with the decrease in the radius above 100 nm, and then it increases markedly with the further decrease in the via radius below 100 nm, which is not consistent with the results obtained by the conventional FEM. It is also shown that as the whole size of the TSV structures is scaled down proportionally, for a given via depth/radius ratio, the peak Mises stresses are almost size scale- independent above 100 nm and exhibit a strong size scale effect below 100 nm.