Stress Of Through Silicon Via Research Articles

The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs

In this work, we discuss the influence of strained silicon technology on transistors in the context of Through Silicon Via (TSV) thermal stress. An accurate thermal stress distribution around a single TSV is firstly obtained by finite element analysis. Then we simulate the transistors using strained silicon technology and apply the TSV–induced stress to the structure to study their magnitudes and mutual influences. We demonstrate that the combined stress distribution of these two stress sources in 45 nm planar transistor cases can almost be viewed as the superposition of each individual distribution results. While in complex 3D structures like the case of FinFETs or the case considering 3D structures in dies, the TSV stress has little impact. Based on the updated stress distribution, the carrier mobility variations of the channels of planar transistors around the TSV are studied. In our experimental setup, the mobility of PMOS is weakened in the x-axis and enhanced in the y-axis, while NMOS has an opposite feature. Besides, the strained silicon technology can greatly enhance the carrier mobility. Finally, we discuss the determination of the keep out zone of a TSV in circuit design based on the aforementioned performance variations of transistors.

Material effect on thermal stress of annular-trench-isolated through silicon via (TSV)

The material effect on the thermal stress of annular-trench-isolated (ATI) through silicon via (TSV) was investigated. The ATI TSV with two sets of materials as the Cu core with the BCB insulator and solder core with parylene-HT insulator were successfully fabricated. A lower stress level was observed for the ATI TSV with a solder core and parylene-HT insulator in experiments and finite element method (FEM) simulation. In order to reveal the origin of the lower stress, the ATI TSVs with different core materials were simulated. The Si ring with high Young’s modulus and low CTE value blocked the effect of the different core material of ATI TSV inside the Si ring and maintained the stress in the Si substrate at the same level. The origin of the lower stress level in the Si substrate was determined to be the lower Young’s modulus and CTE of insulator Parylene-HT than BCB. Due to the surrounding structure of the Si ring, the effect of different core material on thermal stress in the Si substrate became weak. The discussion of the material effect on the thermal stress of ATI TSV provided further understanding of the structure with the Si ring.

Reduction of Thermal Stress in Copper TSV due to Annealing by Low TEC Copper

Introduction Copper through-silicon via (TSV) is the key technology used in 3D packaging. However, the large mismatch in thermal expansion coefficient (TEC) between copper and silicon generates the thermomechanical stress inside and surround the TSV during fabrication process. This thermomechanical stress changes the carrier mobility1 and causes extrusion of copper2. In this study, thermomechanical stress in copper TSV, as well as copper extrusion were reduced using low TEC copper. Moreover, conventional copper TSV was also studied as a comparison. Results and Discussion Fig. 1 shows TEC measurement results of conventional copper and copper electrodeposited with different concentrations of 2M5S leveler. The expansion length of conventional copper (line a) is linear with temperature. Copper pipes electrodeposited with 2M5S leveler (line b, c, and d) start to shrink at 120oC. The reason for the shrinkage of copper is the diffusion of carbon out of copper lattices3. Furthermore, at a 2M5S leveler concentration of 1 ppm, the expansion length of electrodeposited copper is lowest. Therefore, 1 ppm of 2M5S leveler is used for TSV filling for the next experiments.Fig. 2 illustrates the cross-sectional views of copper TSVs after annealing at 500oC. Fig. 2a and 2b are conventional copper TSV. Fig. 2c is low TEC copper TSV (TSV filled with 1 ppm of 2M5S leveler). In Fig. 2a, cracks occur at the vias bottom. Wang found that the stress at the via bottom was very high by simulation using ANSYS4. That large stress is the cause of the cracks at the bottom of the TSV. In Fig. 2b, the extrusion height of conventional copper is about 1.5 µm. In Fig. 2c of low TEC copper TSV, no cracks are observed at the vias bottom. Moreover, the copper extrusion height is only 0.3 µm. Therefore, the stress as well as the extrusion of copper in TSV have been reduced by using low TEC copper. References S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, IEEE Trans. Electron Devices, 53, 1010–1020 (2006).A. Heryanto et al., J. Electron. Mater., 41, 2533–2542 (2012).V. Q. Dinh and K. Kondo, ECS J. Solid State Sci. Technol., 6, P566–P569 (2017).J.-S. Hwang, S.-H. Seo, and W.-J. Lee, J. Electron. Packag., 138, 31006 (2016). Figure 1

Reduction of Thermal Stress in Copper TSV due to Annealing by Low TEC Copper

Copper through-silicon via (TSV) is the key technology used in 3D packaging. During the fabrication process, copper TSV is exposed to a high temperature between 400°C and 600°C. For conventional copper TSV, we observed the cracks at the bottom of TSV after annealing at 500°C and a very high copper extrusion height, which destroys the overlying layers above the TSV. We also succeeded to prevent cracks at the bottom of the TSV and reduce the copper extrusion height by using the low thermal expansion coefficient (TEC) copper.

Residual stress investigation of via-last through-silicon via by polarized Raman spectroscopy measurement and finite element simulation

The residual stresses induced around through-silicon vias (TSVs) by a fabrication process is one of the major concerns of reliability. We proposed a methodology to investigate the residual stress in a via-last TSV. Firstly, radial and axial thermal stresses were measured by polarized Raman spectroscopy. The agreement between the simulated stress level and measured results validated the detail simulation model. Furthermore, the validated simulation model was adopted to the study of residual stress by element death/birth methods. The residual stress at room temperature concentrates at passivation layers owing to the high fabrication process temperatures of 420 °C for SiN film and 350 °C for SiO2 films. For a Si substrate, a high-level stress was observed near potential device locations, which requires attention to address reliability concerns in stress-sensitive devices. This methodology of residual stress analysis can be adopted to investigate the residual stress in other devices.

Wet Metallization of High Aspect Ratio TSV Using Electrografted Polymer Insulator to Suppress Residual Stress in Silicon

Through-silicon-vias (TSV) are the key to 3-D integrated microsystems. Their fabrication leads to reliability issues linked to the thermo-mechanical stress induced in the silicon around the vias. In this paper, we propose reducing the silicon residual stress in high aspect ratio copper TSVs (HAR TSV) using an electrografted polymer insulator, poly-4-vinylpyridine (P4VP), to replace the traditional silicon oxide layer. We use Raman spectroscopy to make the first investigation of the residual stress in the Si around P4VP-insulated TSVs and compare it to SiO2-insulated TSVs. The results show that P4VP acts as a stress buffer layer because of its particular mechanical properties as the measured residual stress in Si is significantly reduced at room temperature around the polymer insulated HAR TSVs. The potential benefits of such a technology are not only better thermo-mechanical reliability of a 3-D integrated microsystem but also greater integration density.

Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging

Through Silicon Via (TSV) technology is a promising and preferred way to realize the reliable interconnection for 3D IC integration. The temperature changed in the processes of TSV manufacturing and chip using, due to the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials used in TSV structure, significant thermal stress will be induced under the thermal load. These stresses may lead to various reliability issues. Dimension parameters and defects are the two factors affecting the thermal behavior of TSV. In order to optimize TSV design and the quality of via filling, a numerical model of Cu-filled TSV was established to simulate and analyze the effect of diameter, aspect ratio (AR) and defects on TSV thermal stress and deformation in this paper. Simulation results show that the equivalent stress and total deformation of TSV increases as the increase of the diameter of TSV. The effect of aspect ratio on equivalent stress is very little; however, it has a great impact on total deformation, especially for the large diameter of the TSV. Additionally, the effects of shape, size and location of defect on thermal stress were also investigated.

Probing Phase Transformations and Microstructural Evolutions at the Small Scales: Synchrotron X-ray Microdiffraction for Advanced Applications in 3D IC (Integrated Circuits) and Solar PV (Photovoltaic) Devices

Synchrotron x-ray microdiffraction (\(\upmu \hbox {XRD}\)) allows characterization of a crystalline material in small, localized volumes. Phase composition, crystal orientation and strain can all be probed in few-second time scales. Crystalline changes over a large areas can be also probed in a reasonable amount of time with submicron spatial resolution. However, despite all the listed capabilities, \(\upmu \hbox {XRD}\) is mostly used to study pure materials but its application in actual device characterization is rather limited. This article will explore the recent developments of the \(\upmu \hbox {XRD}\) technique illustrated with its advanced applications in microelectronic devices and solar photovoltaic systems. Application of \(\upmu \hbox {XRD}\) in microelectronics will be illustrated by studying stress and microstructure evolution in Cu TSV (through silicon via) during and after annealing. The approach allowing study of the microstructural evolution in the solder joint of crystalline Si solar cells due to thermal cycling will be also demonstrated.

Correlation of Through-silicon Via (TSV) Dimension Scaling to TSV Stress and Reliability for 3D Interconnects

Abstract Through-silicon vias (TSVs) are a crucial technology for enabling full three dimensional integration, yet they pose unique reliability risks, including thermal stress buildup due to the mismatch in the coefficient of thermal expansion between the silicon and the copper and the via extrusion phenomena. These effects can degrade device performance and it has been proposed that smaller TSV dimensions will reduce these reliability risks. In this paper, the correlation of shrinking dimensions to TSV stress and reliability is investigated, focusing on the effect of the microstructure on the plasticity and extrusion for 10, 5, and 2 μm diameter copper vias. Synchrotron x-ray microdiffraction revealed local plasticity concentrated in the tops of the vias of all diameters, and showed that the TSV stress behavior seemed to depend on the variations in the grain structure. Electron backscatter diffraction quantified the microstructure to show a tight distribution of grain sizes after the post-plating anneal, but further annealing to 400°C causes considerable data scatter for vias of all diameters. This result is consistent with the observed via extrusion statistics, in which the absolute values and variations in the extrusion heights increased significantly with further annealing. The wafer curvature technique is also used to observe the TSV stress relaxation behavior. Overall, these results suggest that scaling down TSV dimensions may not improve the stress and reliability behavior, particularly after further annealing at 400°C. Since such annealing processes are required for via-middle fabrication, it seems that via reliability will continue to be a challenge as TSV scaling continues.

Performance and Reliability Impact of Copper Plasticity in Backside TSV-Last Fabrication Process

The effects of copper permanent deformation during thermal cycles in backside through-silicon via (TSV)-last fabrication process are studied using an advanced 3-D simulator. The plasticity and creep model parameters are chosen to match experimental data. Two sets of different TSV configurations and back end of line (BEOL) layouts are utilized to examine TSV reliability, BEOL reliability, and front-end device performance after postplating thermal excursion. The results indicate that the copper plasticity deformation affects TSV stress distributions for TSV-last fabrication process. The configuration employing a thicker liner made of a softer material shows better TSV and BEOL reliability and lower TSV stress-induced device performance impact. It is also observed that the BEOL layout near the TSV edge needs to be optimized as the BEOL structures in this region experience larger mechanical stress and lower reliability.

Influence of Copper Pumping on Integrity and Stress of Through-Silicon Vias

The influence of copper pumping on through-silicon vias (TSVs) under thermal loading was investigated using an in situ experimental technique. The morphology of the TSV and its evolution with temperature were observed by scanning electric microscopy, and the process of copper pumping and its damage to the integrity of the TSV were recorded. Some new failure modes were found. The maximum height of pumped copper was as high as $5~\mu \text{m}$ for a single thermal cycle and 25 $\mu \text{m}$ for multiple cycles. The thermal stress of the TSV and its evolution with temperature were then evaluated using a microinfrared photoelastic system. Full-field and real-time measurements were carried out. It was found that copper pumping at high temperature served to release stress and that this stress-free state of the TSV could be maintained. After cooling or annealing, however, the TSV stress again increased.

On the Mechanical Stresses of Cu Through-Silicon Via (TSV) Samples Fabricated by SK Hynix vs. SEMATECH – Enabling Robust and Reliable 3-D Interconnect/Integrated Circuit (IC) Technology

One of the key enablers for the successful integration of 3-D interconnects using the Through-Silicon Via (TSV) schemes is the control of the mechanical stresses in the Cu TSV itself as well as in the surrounding silicon substrate. The synchrotron-sourced X-ray microdiffraction technique has been recognized to allow some important advantages compared to other techniques in characterization of the mechanical stresses in a TSV sample. This approach have been used to study Cu TSV samples from SK Hynix, Inc. earlier as well as more recently from SEMATECH, and we have found interesting differences in the stress states of the Cu TSV. We proposed a possible explanation of the observed differences. This fundamental understanding could lead to improved stress control and hence reliability in the Cu TSV samples, as well as to reduce its impact to the silicon electron mobility and hence to device performance in general.

Process Development and Optimization for 3 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 ${\mu }\text{m}$ top entrant critical dimension and 50 ${\mu }\text{m}$ depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 ${\mu }\text{m}$ TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating.

A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

In 3-D ICs, through silicon via (TSV)-induced thermal residual stress impacts several transistor electrical parameters—low-field mobility, saturation velocity, and threshold voltage. These thermal-stress related shifts are coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing. A biaxial stress model is built, based on a superposition of 2-D axisymmetric and Boussinesq-type elasticity models. The computed stresses and strains are then employed to evaluate transistor mobility, saturation velocity, and threshold voltage. The electrical variations are translated into gate-level delay and leakage power calculations, which are then elevated to circuit-level analysis to thoroughly evaluate the variations in circuit performance-induced by TSV stress.

Induced thermo-mechanical reliability of copper-filled TSV interposer by transient selective annealing technology

Managing the stability of related processes in the integrated manufacturing of three-dimensional integrated circuits (3D-ICs) remains unresolved, especially with regard to the thermo-mechanical behavior of copper filled through silicon via (TSV) interposer during annealing. In this work, transient annealing is successfully applied on the filled copper using only one form of selective heating technology. To address the integration problem, transient thermo-structural coupling analysis using a nonlinear finite element simulation is proposed. Compared with the experimental data, the proposed simulation is found to be highly reliable. Analytical results show that temperature decreases from the top surface of the TSV to other regions within a silicon-based TSV interposer. Stress-induced fracture is common among bonded films, thereby worsening the subsequent mechanical reliability of 3D-IC devices. Moreover, the extent of keep-out zone induced by residual stress of Cu-filled TSV is also defined through the simulation-based mobility gain of nano-scaled devices. In accordance with the results of this investigation, an improvement can be obtained by optimizing the fabrication parameters during annealing. The proposed technology provides a high throughput and reliable processes in TSV manufacturing.

Nondestructive Measurement of the Residual Stresses in Copper Through-Silicon Vias Using Synchrotron-Based Microbeam X-Ray Diffraction

In this paper, we report a new method for achieving depth resolved determination of the full stress tensor in buried Cu through-silicon vias (TSVs), using a synchrotron-based X-ray microdiffraction technique. Two adjacent Cu TSVs were analyzed; one capped with SiO2 (0.17 \(\mu \) m) and the other without. The uncapped Cu TSV was found to have higher stresses with an average hydrostatic stress value of \(145\pm 37\) MPa, as compared with the capped Cu TSV, which had a value of \(89\pm 28\) MPa. Finite element-based parametric analyses of the effect of cap thickness on TSV stress were also performed. The differences in the stresses in the adjacent Cu TSVs were attributed to their microstructural differences and not to the presence of a cap layer. Based on the experimentally determined stresses, the stresses in the surrounding Si for both Cu TSVs were calculated and the FinFET keep-out-zone (KOZ) from the Cu TSV was estimated. The FinFET KOZ is influenced by the microstructural variations in their neighboring Cu TSVs, thus, it should be accounted for in KOZ design rules.

용융 금속 TSV 충전을 위한 저열팽창계수 SiC 복합 충전 솔더의 개발

Among through silicon via (TSV) technologies, for replacing Cu filling method, the method of molten solder filling has been proposed to reduce filling cost and filling time. However, because Sn alloy which has a high coefficient of thermal expansion (CTE) than Cu, CTE mismatch between Si and molten solder induced higher thermal stress than Cu filling method. This thermal stress can deteriorate reliability of TSV by forming defects like void, crack and so on. Therefore, we fabricated SiC composite filling material which had a low CTE for reducing thermal stress in TSV. To add SiC nano particles to molten solder, ball-typed SiC clusters, which were formed with Sn powders and SiC nano particles by ball mill process, put into molten Sn and then, nano particle-dispersed SiC composite filling material was produced. In the case of 1 wt.% of SiC particle, the CTE showed a lowest value which was a <TEX>$14.8ppm/^{\circ}C$</TEX> and this value was lower than CTE of Cu. Up to 1 wt.% of SiC particle, Young's modulus increased as wt.% of SiC particle increased. And also, we observed cross-sectioned TSV which was filled with 1 wt.% of SiC particle and we confirmed a possibility of SiC composite material as a TSV filling material.

The Thermal Stress Analysis for IC Integrations with TSV Interposer by Complement Sector Models

The thermal stress of typical integrated circuit (IC) integration with the interposer of through silicon via (TSV) was investigated in this study. To overcome the huge computational costs due to meshing the large amount of TSVs’ microstructures, a simplified method, i.e. the complement sector model, was proposed and verified by the symmetric 1/8th full model. Using the sector model, the parametric studies were carried out to reveal the critical locations of TSV and the crucial parameters. Furthermore, statistical methods were invoked to clarify the impact of the major parameters, such as the modulus and coefficient of thermal expansion of underfill materials, the pitch and diameter of TSV, etc. Upon the analysis results, the design of minimized stress in TSV for the IC integration with TSV interposer was achieved.

Analysis of High Aspect Ratio through Silicon via (TSV) Diffusion and Stress Impact Profile during 3D Advanced Integration

In order to overcome the performances, dimensions and cost limit beyond the 22 nm technology node, three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution. Another potential of the TSVs is their promises in enabling advanced multi-level chips, integrating heterogeneous CMOS technologies with emerging technologies such as MEMS and bio-chips.As many integration schemes include the need of high aspect ratio TSVs in order to increase silicon thickness for Die bow and warp limitations or decrease TSV diameter for density increase, TSV Metallization, particularly barrier and seed layer deposition, has become a critical process step of the integration. In a previous work, the investigation of a low temperature (200°C) MOCVD TiN film as a barrier layer to prevent copper diffusion was studied. From these studies, it comes out that even a 5nm thin TiN film withstand barrier efficiency thermal test on fullsheet deposition. This barrier shows up a different behavior while being integrated in the high aspect ratio TSV due to subsequent plasma treatment during the deposition. Actually, the plasma densification does not have the same efficiency through the sidewall of the 80 µm deep TSV thereby enabling a different material structure all along the profile of the via. Characterizations of the behavior of the barrier in the TSV then become a great challenge in order to handle the integration protocol both in horizontal and vertical scales. Working at this scale of topology makes standard diffusion methods limited to evaluate the intrinsic diffusion properties into the via. A localized diffusion methods using Tof-SIMS along the sidewall of the TSV was used to overcome these geometrical issues (figure 1). This technique allowed us to compare different type of barriers and the determination of the minimal thickness for the efficiency of these films as a barrier in the TSV.3-D stacking using TSV involves mechanical and thermal stresses in the Cu TSV itself as well as in the surrounding silicon substrate. As the Cu volume of the TSV becomes important compared to the size of the active components, stresses are induced extrinsically by the interaction of every metallurgical step of the TSV elaboration, including dielectric isolation, barrier/seed layer and copper filling depositions as well as subsequent copper anneals. Stresses can be induced intrinsically by thermal treatment due to the mismatch of thermal expansion between the via material and Si. Usually the X-rays diffraction (XRD) and the stress distribution from the variation of the curvature during the processing is used to measure the stress induced in thin films. Due to the depth of the structure, these methods are limited to measure the stress generated by the TSV.Micro Raman spectroscopy measurements allow measuring the stress induced by every single metallurgical step of the TSV elaboration. For the barrier layer step, the intrinsic stress generated into the silicon by different types of TiN barrier according to process parameters and subsequent plasma treatment were measured and compared (Figure 2). It comes out that some barriers induced a more compressive stress in the silicon and others seem to have a tensile behavior. Then the evolution of the stress of the TSV through different anneal conditions were studied to evaluate the stability of the via with the temperature.

수치해석에 의한 TSV 구조의 열응력 및 구리 Protrusion 연구

Through-Silicon Via (TSV) 기술은 3차원 적층 패키징를 위한 핵심 기술로서 큰 관심을 받고 있다. 그러나 TSV 기술은 아직 다양한 공정상의 문제와 신뢰성 문제를 해결해야 하는 난제가 남아 있다. 특히 구리 비아(via)와 실리콘 기판의 큰 열팽창계수의 차이로 인한 열응력은 계면 박리, 크랙 발생, 구리 protrusion 등 다양한 신뢰성 문제를 발생시킨다. 본 연구에서는 구리 TSV 구조의 열응력을 수치해석을 이용하여 분석하였으며, 3차원 TSV 비아와 실리콘 기판의 응력 및 변형을 해석하였다. 비아의 크기, 비아와 비아 사이의 간격 및 비아의 밀도가 TSV 구조의 응력에 미치는 영향을 분석하였으며, 또한 어닐링(annealing) 온도 및 비아의 크기가 구리 protrusion에 미치는 영향을 관찰하였다. 구리 TSV 구조의 신뢰성을 향상시키기 위해서는 적절한 비아와 비아 사이의 간격을 유지한 상태에서, 비아의 크기 및 비아의 밀도는 작아야 한다. 또한 구리 protrusion을 감소시키기 위해서는 비아의 크기 및 어닐링 공정과 같은 공정의 온도를 낮추어야 한다. 본 연구의 결과는 TSV 구조의 열응력과 관련된 신뢰성 이슈를 이해하고, TSV 구조의 설계 가이드라인을 제공하는데 도움을 줄 수 있을 것으로 판단된다. The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.